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-rw-r--r--src/soc/amd/common/block/cpu/car/cache_as_ram.S11
-rw-r--r--src/soc/amd/common/block/cpu/noncar/pre_c.S2
-rw-r--r--src/soc/example/min86/cache_as_ram.S2
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram.S2
-rw-r--r--src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S2
-rw-r--r--src/soc/intel/quark/bootblock/esram_init.S2
6 files changed, 20 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index 3eb7670784..6282d7e571 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -8,9 +8,16 @@
******************************************************************************
*/
-#include "gcccar.inc"
#include <cpu/x86/post_code.h>
+.section .init
+
+.code32
+
+_cache_as_ram_setup:
+
+#include "gcccar.inc"
+
/*
* on entry:
* mm0: BIST (ignored)
@@ -43,3 +50,5 @@ before_carstage:
post_code(POST_DEAD_CODE)
hlt
jmp .halt_forever
+
+_cache_as_ram_setup_end:
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index 6fae1ed1cb..520e3c08b0 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -2,6 +2,8 @@
#include <cpu/x86/post_code.h>
+.section .init, "ax", @progbits
+
.global bootblock_resume_entry
bootblock_resume_entry:
post_code(0xb0)
diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S
index a350143834..5c5066d7ea 100644
--- a/src/soc/example/min86/cache_as_ram.S
+++ b/src/soc/example/min86/cache_as_ram.S
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+.section .init, "ax", @progbits
+
.global bootblock_pre_c_entry
.code32
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index aaf6af7d5a..49b40a8d9a 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -9,6 +9,8 @@
#include <rules.h>
#include <intelblocks/msr.h>
+.section .init, "ax", @progbits
+
.code32
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 04dc5331e1..a2e85b9aac 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -10,6 +10,8 @@
#define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4)
#define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4)
+.section .init, "ax", @progbits
+
.extern temp_ram_init_params
.global bootblock_pre_c_entry
diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S
index fc1c7c903f..39ce7bd02d 100644
--- a/src/soc/intel/quark/bootblock/esram_init.S
+++ b/src/soc/intel/quark/bootblock/esram_init.S
@@ -71,6 +71,8 @@
.equ CFGNONSTICKY_W1_OFFSET, (0x52)
.equ FORCE_WARM_RESET, (0x00000001)
+.section .init, "ax", @progbits
+
.global bootblock_pre_c_entry
bootblock_pre_c_entry: