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-rw-r--r--src/soc/intel/broadwell/cpu.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 00460c6282..694c7277a4 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -290,6 +290,28 @@ static void configure_c_states(void)
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
+static void configure_thermal_target(void)
+{
+ config_t *conf;
+ struct device *lapic;
+ msr_t msr;
+
+ /* Find pointer to CPU configuration */
+ lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+ if (!lapic || !lapic->chip_info)
+ return;
+ conf = lapic->chip_info;
+
+ /* Set TCC activation offset if supported */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+ msr = rdmsr(MSR_TEMPERATURE_TARGET);
+ msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+ msr.lo |= (conf->tcc_offset & 0xf) << 24;
+ wrmsr(MSR_TEMPERATURE_TARGET, msr);
+ }
+}
+
static void configure_misc(void)
{
msr_t msr;
@@ -372,7 +394,7 @@ static void cpu_core_init(struct device *cpu)
configure_misc();
/* Thermal throttle activation offset */
- configure_tcc_thermal_target();
+ configure_thermal_target();
/* Enable Direct Cache Access */
configure_dca_cap();