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-rw-r--r--src/soc/intel/skylake/chip.c2
-rw-r--r--src/soc/intel/skylake/chip.h6
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index b24ec4fdc0..e0baefcdda 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -188,6 +188,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));
+ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
+ params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
/*
* PcieRpClkSrcNumber UPD is set to clock source number(0-6) for
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index d268eebd66..d4afa1de64 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -284,6 +284,12 @@ struct soc_intel_skylake_config {
/* Enable/Disable HotPlug support for Root Port */
u8 PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
+ /* PCIE RP Max Payload, Max Payload Size supported */
+ enum {
+ RpMaxPayload_128,
+ RpMaxPayload_256,
+ } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
+
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];