diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 40 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 25 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/serialio.h | 43 |
3 files changed, 108 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index ab546337e4..42a59ceec4 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -86,6 +86,43 @@ static const char *soc_acpi_name(struct device *dev) } #endif +static void parse_devicetree(FSP_S_CONFIG *params) +{ + struct device *dev = SA_DEV_ROOT; + if (!dev) { + printk(BIOS_ERR, "Could not find root device\n"); + return; + } + + const config_t *config = dev->chip_info; + const int SerialIoDev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 + }; + + for (int i = 0; i < ARRAY_SIZE(SerialIoDev); i++) { + dev = dev_find_slot(0, SerialIoDev[i]); + if (!dev->enabled) { + params->SerialIoDevMode[i] = PchSerialIoDisabled; + continue; + } + params->SerialIoDevMode[i] = PchSerialIoPci; + if (config->SerialIoDevMode[i] == PchSerialIoAcpi || + config->SerialIoDevMode[i] == PchSerialIoHidden) + params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; + } +} + void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -137,6 +174,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) const struct device *dev = SA_DEV_ROOT; const config_t *config = dev->chip_info; + /* Parse device tree and enable/disable devices */ + parse_devicetree(params); + /* Set USB OC pin to 0 first */ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { params->Usb2OverCurrentPin[i] = 0; diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 52a5fc13a3..6d16327f27 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,6 +20,7 @@ #include <intelblocks/gspi.h> #include <stdint.h> +#include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> @@ -200,6 +201,30 @@ struct soc_intel_cannonlake_config { */ uint32_t PrmrrSize; uint8_t PmTimerDisabled; + /* + * SerialIO device mode selection: + * + * Device index: + * PchSerialIoIndexI2C0 + * PchSerialIoIndexI2C1 + * PchSerialIoIndexI2C2 + * PchSerialIoIndexI2C3 + * PchSerialIoIndexI2C4 + * PchSerialIoIndexI2C5 + * PchSerialIoIndexSPI0 + * PchSerialIoIndexSPI1 + * PchSerialIoIndexSPI2 + * PchSerialIoIndexUART0 + * PchSerialIoIndexUART1 + * PchSerialIoIndexUART2 + * + * Mode select: + * PchSerialIoDisabled + * PchSerialIoPci + * PchSerialIoAcpi + * PchSerialIoHidden + */ + uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h new file mode 100644 index 0000000000..e152770024 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SERIALIO_H_ +#define _SERIALIO_H_ + +typedef enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoAcpi, + PchSerialIoHidden, +} PCH_SERIAL_IO_MODE; + +typedef enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, + PchSerialIoIndexSPI0, + PchSerialIoIndexSPI1, + PchSerialIoIndexSPI2, + PchSerialIoIndexUART0, + PchSerialIoIndexUART1, + PchSerialIoIndexUART2, + PchSerialIoIndexMAX +} PCH_SERIAL_IO_CONTROLLER; + +#endif |