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-rw-r--r--src/soc/intel/tigerlake/chip.h3
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c5
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index a3319d4ee4..fe338352fb 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -107,6 +107,9 @@ struct soc_intel_tigerlake_config {
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
+ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
+
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 5acad201c6..fc2a3c026a 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -151,6 +151,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpAdvancedErrorReporting[i] =
config->PcieRpAdvancedErrorReporting[i];
}
+
+ /* Enable ClkReqDetect for enabled port */
+ memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
+ sizeof(config->PcieRpClkReqDetect));
+
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (dev) {