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-rw-r--r--src/soc/intel/tigerlake/chip.h12
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c9
2 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index d9283e1652..e6e106df94 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -288,6 +288,18 @@ struct soc_intel_tigerlake_config {
/* HyperThreadingDisable : Yes (1) / No (0) */
uint8_t HyperThreadingDisable;
+
+ /*
+ * Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
+ * Default 0. Setting this to 1 disables the DMI Power Optimizer.
+ */
+ uint8_t DmiPwrOptimizeDisable;
+
+ /*
+ * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
+ * Default 0. Setting this to 1 disables the SATA Power Optimizer.
+ */
+ uint8_t SataPwrOptimizeDisable;
};
typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 11d79529ed..73c41c8519 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -184,6 +184,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsDevSlp));
}
+ /*
+ * Power Optimizer for DMI and SATA.
+ * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0.
+ * Boards not needing the optimizers explicitly disables them by setting
+ * these disable variables to 1 in devicetree overrides.
+ */
+ params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
+ params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
+
/* LAN */
dev = pcidev_path_on_root(PCH_DEVFN_GBE);
if (!dev)