diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/reset.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/spi.h | 4 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/include/soc/memlayout.ld | 2 | ||||
| -rw-r--r-- | src/soc/samsung/exynos5420/include/soc/setup.h | 2 |
8 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h index 93489bb8d4..7e233fa2d4 100644 --- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h +++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h @@ -38,7 +38,7 @@ #endif /* GET & SET */ /*************************************************************************** - *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Comand control registers + *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Command control registers ***************************************************************************/ #define DDR34_CORE_PHY_CONTROL_REGS_REVISION 0x00000000 /* Address & Control revision register */ #define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS 0x00000004 /* PHY PLL status register */ diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index 26f0a632a0..140fbff6a5 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -74,7 +74,7 @@ static int send_heci_reset_message(void) printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n"); return -1; } - printk(BIOS_DEBUG, "Heci recieve success!\n"); + printk(BIOS_DEBUG, "Heci receive success!\n"); return 0; } diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 8651297905..4b531177f4 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -443,7 +443,7 @@ int heci_receive(void *buff, size_t *maxlen) do { received = recv_one_message(&hdr, p, left); if (!received) { - printk(BIOS_ERR, "HECI: Failed to recieve!\n"); + printk(BIOS_ERR, "HECI: Failed to receive!\n"); return 0; } left -= received; diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 4c88ed55bf..26ea56a93a 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -124,7 +124,7 @@ static void soc_config_tco(void) pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); /* Program TCO Base */ - pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); + pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDRESS); /* Enable TCO in SMBUS */ pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN); @@ -133,7 +133,7 @@ static void soc_config_tco(void) * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] * to [SMBUS PCI offset 50h[15:5], 1]. */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1)); + pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDRESS | (1 << 1)); /* Program TCO timer halt */ tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index f2fde715f7..475d79db71 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -87,7 +87,7 @@ #define ACPI_BASE_ADDRESS 0x1800 #define ACPI_BASE_SIZE 0x100 -#define TCO_BASE_ADDDRESS 0x400 +#define TCO_BASE_ADDRESS 0x400 #define TCO_BASE_SIZE 0x20 #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index 0e1847c985..ce5de83c62 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -101,9 +101,9 @@ check_member(rockchip_spi, rxdr, 0x800); /* SSN to Sclk_out delay */ #define SPI_SSN_DELAY_OFFSET 10 #define SPI_SSN_DELAY_MASK 0x1 -/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */ +/* the period between ss_n active and sclk_out active is half sclk_out cycles */ #define SPI_SSN_DELAY_HALF 0x00 -/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */ +/* the period between ss_n active and sclk_out active is one sclk_out cycle */ #define SPI_SSN_DELAY_ONE 0x01 /* Serial Endian Mode */ diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index 1f13bb9e62..bc5d0669da 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -26,7 +26,7 @@ SECTIONS { SRAM_START(0x2020000) /* 17K hole, includes BL1 */ - /* Bootblock is preceeded by 16 byte variable length BL2 checksum. */ + /* Bootblock is preceded by 16 byte variable length BL2 checksum. */ BOOTBLOCK(0x2024410, 32K - 16) /* 15K hole */ ROMSTAGE(0x2030000, 128K) diff --git a/src/soc/samsung/exynos5420/include/soc/setup.h b/src/soc/samsung/exynos5420/include/soc/setup.h index f024a2df45..139f5b756a 100644 --- a/src/soc/samsung/exynos5420/include/soc/setup.h +++ b/src/soc/samsung/exynos5420/include/soc/setup.h @@ -729,7 +729,7 @@ struct exynos5_phy_control; #define CTRL_RDLAT_OFFSET 0 #define CMD_DEFAULT_LPDDR3 0xF -#define CMD_DEFUALT_OFFSET 0 +#define CMD_DEFAULT_OFFSET 0 #define T_WRDATA_EN 0x7 #define T_WRDATA_EN_DDR3 0x8 /* FIXME(dhendrix): 6 for DDR3? see T_wrdata_en */ #define T_WRDATA_EN_OFFSET 16 |