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-rw-r--r--src/soc/imgtec/pistachio/include/soc/cpu.h12
-rw-r--r--src/soc/imgtec/pistachio/monotonic_timer.c19
2 files changed, 24 insertions, 7 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h
index 72775b5cbe..89952197f7 100644
--- a/src/soc/imgtec/pistachio/include/soc/cpu.h
+++ b/src/soc/imgtec/pistachio/include/soc/cpu.h
@@ -18,14 +18,18 @@
#ifndef __SOC_IMGTEC_DANUBE_CPU_H__
#define __SOC_IMGTEC_DANUBE_CPU_H__
+#include <arch/io.h>
+
#define IMG_SPIM0_BASE_ADDRESS 0xB8100F00
#define IMG_SPIM1_BASE_ADDRESS 0xB8101000
/*
- * Reading at this address allows to identify the platform the code is running
- * on.
+ * This register holds the FPGA image version
+ * If we're not working on the FPGA this will be 0
*/
-#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060))
-#define IMG_PLATFORM_ID_SILICON 0xF00D0006
+#define PRIMARY_FPGA_VERSION 0xB8149060
+#define IMG_PLATFORM_ID() read32(PRIMARY_FPGA_VERSION)
+#define IMG_PLATFORM_ID_FPGA 0xD1400003 /* Last FPGA image */
+#define IMG_PLATFORM_ID_SILICON 0
#endif
diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c
index 99c147b7c2..c2408b0649 100644
--- a/src/soc/imgtec/pistachio/monotonic_timer.c
+++ b/src/soc/imgtec/pistachio/monotonic_timer.c
@@ -23,6 +23,9 @@
#include <arch/cpu.h>
#include <soc/cpu.h>
+#define PISTACHIO_CLOCK_SWITCH 0xB8144200
+#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
+
static int get_count_mhz_freq(void)
{
static unsigned count_mhz_freq;
@@ -30,10 +33,20 @@ static int get_count_mhz_freq(void)
if (!count_mhz_freq) {
if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
count_mhz_freq = 25; /* FPGA board */
- /*
- * Will need some means of finding out the counter
- * frequency on a real SOC
+ else {
+ /* If MIPS PLL external bypass bit is set, it means
+ * that the MIPS PLL is already set up to work at a
+ * frequency of 550 MHz; otherwise, the crystal is
+ * used with a frequency of 52 MHz
*/
+ if (read32(PISTACHIO_CLOCK_SWITCH) &
+ MIPS_EXTERN_PLL_BYPASS_MASK)
+ /* Half MIPS PLL freq. */
+ count_mhz_freq = 275;
+ else
+ /* Half Xtal freq. */
+ count_mhz_freq = 26;
+ }
}
return count_mhz_freq;
}