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-rw-r--r--src/soc/intel/cannonlake/chip.h2
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2923efc555..e5ceac9312 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -185,6 +185,8 @@ struct soc_intel_cannonlake_config {
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
/* PCIe LTR(Latency Tolerance Reporting) mechanism */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+ /* Implemented as slot or built-in? */
+ uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
/* Enable/Disable HotPlug support for Root Port */
uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0779ce2e44..51ed2a8b57 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -479,6 +479,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
+ memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
+ sizeof(config->PcieRpSlotImplemented));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));