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-rw-r--r--src/soc/intel/baytrail/gfx.c2
-rw-r--r--src/soc/intel/baytrail/lpss.c3
-rw-r--r--src/soc/intel/baytrail/romstage/raminit.c2
-rw-r--r--src/soc/intel/baytrail/scc.c2
-rw-r--r--src/soc/intel/braswell/gfx.c2
-rw-r--r--src/soc/intel/braswell/lpss.c3
-rw-r--r--src/soc/intel/broadwell/sata.c3
7 files changed, 10 insertions, 7 deletions
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 0da1fe49d3..0ee3cef591 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -205,7 +205,7 @@ static const struct reg_script gfx_init_script[] = {
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
- REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
+ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
/* Display */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index 08c3c05d85..afeb687be8 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
- REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
+ REG_PCI_OR16(PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 0b7a8c646d..7e6bcaba0f 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -36,7 +36,7 @@ int smbus_enable_iobar(uintptr_t base)
pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg);
/* Enable decode of I/O space. */
reg = pci_read_config16(smbus_dev, PCI_COMMAND);
- reg |= 0x1;
+ reg |= PCI_COMMAND_IO;
pci_write_config16(smbus_dev, PCI_COMMAND, reg);
/* Enable Host Controller */
reg = pci_read_config8(smbus_dev, 0x40);
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index f178e83d28..3b19f1b277 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -74,7 +74,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR16(PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg,
SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN),
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index 1bd0033313..7599329b61 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -14,7 +14,7 @@
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
- REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
+ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
REG_SCRIPT_END
};
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 7ff42c35df..961d405156 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
- REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
+ REG_PCI_OR16(PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index 5ddccc52f0..e7135f79b0 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -36,7 +36,8 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
/* Enable BARs */
- pci_write_config16(dev, PCI_COMMAND, 0x0007);
+ pci_write_config16(dev, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* Set Interrupt Line */
/* Interrupt Pin is set by D31IP.PIP */