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-rw-r--r--src/soc/rockchip/rk3288/bootblock.c11
-rw-r--r--src/soc/rockchip/rk3288/memlayout.ld3
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index eec3456613..b2f5bd9553 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -17,10 +17,12 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/cache.h>
#include <arch/io.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <soc/rockchip/rk3288/grf.h>
+#include <symbols.h>
#include "addressmap.h"
#include "timer.h"
#include "clock.h"
@@ -41,4 +43,13 @@ static void bootblock_cpu_init(void)
}
rkclk_init();
+
+ mmu_init();
+ /* Start with a clean slate. */
+ mmu_config_range(0, 4096, DCACHE_OFF);
+ /* SRAM is tightly wedged between registers, need to use subtables. Map
+ * write-through as equivalent for non-cacheable without XN on A17. */
+ mmu_config_range_kb((uintptr_t)_sram/KiB,
+ _sram_size/KiB, DCACHE_WRITETHROUGH);
+ dcache_mmu_enable();
}
diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld
index 6faec63ba5..2ddb6a6077 100644
--- a/src/soc/rockchip/rk3288/memlayout.ld
+++ b/src/soc/rockchip/rk3288/memlayout.ld
@@ -34,7 +34,8 @@ SECTIONS
SRAM_START(0xFF700000)
TTB(0xFF700000, 16K)
- BOOTBLOCK(0xFF704004, 16K - 4)
+ BOOTBLOCK(0xFF704004, 15K - 4)
+ TTB_SUBTABLES(0xFF707c00, 1K)
VBOOT2_WORK(0xFF708000, 16K)
OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K)
PRERAM_CBFS_CACHE(0xFF716000, 4K)