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-rw-r--r--src/soc/intel/cannonlake/fsp_params.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 06c556ca74..4038335787 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -421,31 +421,29 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
tconfig->PchLockDownBiosInterface = 0;
params->PchLockDownBiosLock = 0;
params->PchLockDownRtcMemoryLock = 0;
+#if CONFIG(SOC_INTEL_COMETLAKE)
/*
- * TODO: Disable SpiFlashCfgLockDown config after FSP provides
- * dedicated UPD
- *
* Skip SPI Flash Lockdown from inside FSP.
* Making this config "0" means FSP won't set the FLOCKDN bit
* of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL).
* So, it becomes coreboot's responsibility to set this bit
* before end of POST for security concerns.
*/
- // params->SpiFlashCfgLockDown = 0;
+ params->SpiFlashCfgLockDown = 0;
+#endif
} else {
tconfig->PchLockDownGlobalSmi = 1;
tconfig->PchLockDownBiosInterface = 1;
params->PchLockDownBiosLock = 1;
params->PchLockDownRtcMemoryLock = 1;
+#if CONFIG(SOC_INTEL_COMETLAKE)
/*
- * TODO: Enable SpiFlashCfgLockDown config after FSP provides
- * dedicated UPD
- *
* Enable SPI Flash Lockdown from inside FSP.
* Making this config "1" means FSP will set the FLOCKDN bit
* of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL).
*/
- // params->SpiFlashCfgLockDown = 1;
+ params->SpiFlashCfgLockDown = 1;
+#endif
}
}