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-rw-r--r--src/soc/intel/tigerlake/chip.h2
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c5
2 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f82f13d45b..1d4bd5fa5a 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -292,6 +292,8 @@ struct soc_intel_tigerlake_config {
*/
uint8_t cpu_ratio_override;
+ /* HyperThreadingDisable : Yes (1) / No (0) */
+ uint8_t HyperThreadingDisable;
};
typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 95f637e4ec..32f1b031a9 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -143,8 +143,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
else
m_cfg->TcssItbtPcie3En = 0;
- /* Enable Hyper Threading */
- m_cfg->HyperThreading = 1;
+ /* Hyper Threading */
+ m_cfg->HyperThreading = !config->HyperThreadingDisable;
+
/* Disable Lock PCU Thermal Management registers */
m_cfg->LockPTMregs = 0;
/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */