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-rw-r--r--src/soc/intel/apollolake/include/soc/heci.h2
-rw-r--r--src/soc/intel/baytrail/include/soc/iomap.h3
-rw-r--r--src/soc/intel/braswell/include/soc/iomap.h3
-rw-r--r--src/soc/intel/cannonlake/include/soc/lpc.h2
-rw-r--r--src/soc/intel/common/block/include/intelblocks/smm.h2
-rw-r--r--src/soc/intel/common/block/include/intelblocks/vmx.h2
-rw-r--r--src/soc/intel/fsp_baytrail/include/soc/iomap.h3
-rw-r--r--src/soc/intel/icelake/include/soc/lpc.h2
-rw-r--r--src/soc/mediatek/mt8173/include/soc/da9212.h2
-rw-r--r--src/soc/mediatek/mt8173/include/soc/mt6311.h2
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/ebi2.h2
-rw-r--r--src/soc/rockchip/rk3399/include/soc/tsadc.h2
12 files changed, 24 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/include/soc/heci.h b/src/soc/intel/apollolake/include/soc/heci.h
index 1151321445..ac28b14cee 100644
--- a/src/soc/intel/apollolake/include/soc/heci.h
+++ b/src/soc/intel/apollolake/include/soc/heci.h
@@ -17,6 +17,8 @@
#ifndef _SOC_APOLLOLAKE_HECI_H_
#define _SOC_APOLLOLAKE_HECI_H_
+#include <stdint.h>
+
enum sec_status {
SEC_STATE_RESET = 0,
SEC_STATE_INIT,
diff --git a/src/soc/intel/baytrail/include/soc/iomap.h b/src/soc/intel/baytrail/include/soc/iomap.h
index bb6b4bbdea..11c01e311d 100644
--- a/src/soc/intel/baytrail/include/soc/iomap.h
+++ b/src/soc/intel/baytrail/include/soc/iomap.h
@@ -16,7 +16,6 @@
#ifndef _BAYTRAIL_IOMAP_H_
#define _BAYTRAIL_IOMAP_H_
-
/*
* Memory Mapped IO bases.
*/
@@ -79,6 +78,8 @@
#define SMBUS_BASE_ADDRESS 0xefa0
#ifndef __ACPI__
+#include <stdint.h>
+
/* Read Top of Low Memory (BMBOUND) */
uint32_t nc_read_top_of_low_memory(void);
#endif
diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h
index a07490280e..c61983b446 100644
--- a/src/soc/intel/braswell/include/soc/iomap.h
+++ b/src/soc/intel/braswell/include/soc/iomap.h
@@ -17,7 +17,6 @@
#ifndef _SOC_IOMAP_H_
#define _SOC_IOMAP_H_
-
/*
* Memory Mapped IO bases.
*/
@@ -81,6 +80,8 @@
#define SMBUS_BASE_ADDRESS 0xefa0
#ifndef __ACPI__
+#include <stdint.h>
+
/* Read Top of Low Memory (BMBOUND) */
uint32_t nc_read_top_of_low_memory(void);
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h
index a4e42bddf3..ea72675dbc 100644
--- a/src/soc/intel/cannonlake/include/soc/lpc.h
+++ b/src/soc/intel/cannonlake/include/soc/lpc.h
@@ -17,6 +17,8 @@
#ifndef _SOC_CANNONLAKE_LPC_H_
#define _SOC_CANNONLAKE_LPC_H_
+#include <stdint.h>
+
/* PCI Configuration Space (D31:F0): LPC */
#define SCI_IRQ_SEL (7 << 0)
#define SCIS_IRQ9 0
diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h
index f560f24e2b..c04ec46800 100644
--- a/src/soc/intel/common/block/include/intelblocks/smm.h
+++ b/src/soc/intel/common/block/include/intelblocks/smm.h
@@ -17,6 +17,8 @@
#ifndef SOC_INTEL_COMMON_BLOCK_SMM_H
#define SOC_INTEL_COMMON_BLOCK_SMM_H
+#include <stdint.h>
+
/*
* This common code block relies on each specific SOC defining the macro
* ENABLE_SMI_PARAMS for the values needed for SMI enabling on the
diff --git a/src/soc/intel/common/block/include/intelblocks/vmx.h b/src/soc/intel/common/block/include/intelblocks/vmx.h
index 7f65b599b4..b93ceeb8c1 100644
--- a/src/soc/intel/common/block/include/intelblocks/vmx.h
+++ b/src/soc/intel/common/block/include/intelblocks/vmx.h
@@ -14,6 +14,8 @@
#ifndef SOC_INTEL_COMMON_BLOCK_VMX_H
#define SOC_INTEL_COMMON_BLOCK_VMX_H
+#include <stdint.h>
+
struct vmx_param {
uint8_t enable;
};
diff --git a/src/soc/intel/fsp_baytrail/include/soc/iomap.h b/src/soc/intel/fsp_baytrail/include/soc/iomap.h
index bb6b4bbdea..11c01e311d 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/iomap.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/iomap.h
@@ -16,7 +16,6 @@
#ifndef _BAYTRAIL_IOMAP_H_
#define _BAYTRAIL_IOMAP_H_
-
/*
* Memory Mapped IO bases.
*/
@@ -79,6 +78,8 @@
#define SMBUS_BASE_ADDRESS 0xefa0
#ifndef __ACPI__
+#include <stdint.h>
+
/* Read Top of Low Memory (BMBOUND) */
uint32_t nc_read_top_of_low_memory(void);
#endif
diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/lpc.h
index df781be54d..dfcfa353c8 100644
--- a/src/soc/intel/icelake/include/soc/lpc.h
+++ b/src/soc/intel/icelake/include/soc/lpc.h
@@ -16,6 +16,8 @@
#ifndef _SOC_ICELAKE_LPC_H_
#define _SOC_ICELAKE_LPC_H_
+#include <stdint.h>
+
/* PCI Configuration Space (D31:F0): LPC */
#define SCI_IRQ_SEL (7 << 0)
#define SCIS_IRQ9 0
diff --git a/src/soc/mediatek/mt8173/include/soc/da9212.h b/src/soc/mediatek/mt8173/include/soc/da9212.h
index 388958d92b..118ba85667 100644
--- a/src/soc/mediatek/mt8173/include/soc/da9212.h
+++ b/src/soc/mediatek/mt8173/include/soc/da9212.h
@@ -16,6 +16,8 @@
#ifndef __SOC_DA9212_H_
#define __SOC_DA9212_H_
+#include <stdint.h>
+
void da9212_probe(uint8_t i2c_num);
enum {
diff --git a/src/soc/mediatek/mt8173/include/soc/mt6311.h b/src/soc/mediatek/mt8173/include/soc/mt6311.h
index 3b0b79a8c7..29063d6fe1 100644
--- a/src/soc/mediatek/mt8173/include/soc/mt6311.h
+++ b/src/soc/mediatek/mt8173/include/soc/mt6311.h
@@ -16,6 +16,8 @@
#ifndef __SOC_MEDIATEK_MT8173_MT6311_H__
#define __SOC_MEDIATEK_MT8173_MT6311_H__
+#include <stdint.h>
+
void mt6311_probe(uint8_t i2c_num);
enum {
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h b/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h
index 1cc04aefad..83030e4df9 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/ebi2.h
@@ -31,6 +31,8 @@
#ifndef __SOC_QUALCOMM_IPQ40XX_EBI2_H_
#define __SOC_QUALCOMM_IPQ40XX_EBI2_H_
+#include <stdint.h>
+
#define EBI2CR_BASE (0x1A600000)
struct ebi2cr_regs {
diff --git a/src/soc/rockchip/rk3399/include/soc/tsadc.h b/src/soc/rockchip/rk3399/include/soc/tsadc.h
index b1f617df75..082a2bc905 100644
--- a/src/soc/rockchip/rk3399/include/soc/tsadc.h
+++ b/src/soc/rockchip/rk3399/include/soc/tsadc.h
@@ -16,6 +16,8 @@
#ifndef __SOC_ROCKCHIP_RK3399_TSADC_H__
#define __SOC_ROCKCHIP_RK3399_TSADC_H__
+#include <stdint.h>
+
enum {
TSHUT_POL_HIGH = 1 << 8,
TSHUT_POL_LOW = 0 << 8