diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/nvidia/tegra132/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/ccplex.c | 132 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/ccplex.h | 6 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/romstage.h | 26 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/power.c | 57 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/power.h | 6 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/romstage.c | 10 |
7 files changed, 231 insertions, 7 deletions
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 8c085a945a..252f1a22dd 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += i2c.c romstage-y += dma.c romstage-y += monotonic_timer.c romstage-y += romstage.c +romstage-y += power.c romstage-y += sdram.c romstage-y += sdram_lp0.c romstage-y += ../tegra/gpio.c diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index b774630797..9f857070e0 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -23,11 +23,15 @@ #include <cbfs.h> #include <timer.h> #include <soc/addressmap.h> +#include <soc/romstage.h> #include "clk_rst.h" #include "ccplex.h" +#include "flow.h" #include "mc.h" #include "pmc.h" +#include "power.h" +#define EVP_CPU_RESET_VECTOR (void *)(uintptr_t)(TEGRA_EVP_BASE + 0x100) #define CLK_RST_REGS (void *)(uintptr_t)(TEGRA_CLK_RST_BASE) #define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE) #define MTS_FILE_NAME "mts" @@ -105,3 +109,131 @@ int ccplex_load_mts(void) return ccplex_start(); } + +static void enable_cpu_clocks(void) +{ + struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS; + uint32_t reg; + + reg = read32(&clk_rst->clk_enb_l_set); + reg |= CLK_ENB_CPU; + write32(reg, &clk_rst->clk_enb_l_set); + + reg = read32(&clk_rst->clk_enb_v_set); + reg |= SET_CLK_ENB_CPUG_ENABLE | SET_CLK_ENB_CPULP_ENABLE; + write32(reg, &clk_rst->clk_enb_v_set); +} + +static void enable_cpu_power_partitions(void) +{ + /* Bring up fast cluster, non-CPU, CPU0, and CPU1 partitions. */ + power_ungate_partition(POWER_PARTID_CRAIL); + power_ungate_partition(POWER_PARTID_C0NC); + power_ungate_partition(POWER_PARTID_CE0); + power_ungate_partition(POWER_PARTID_CE1); +} + + +static void request_ram_repair(void) +{ + struct flow_ctlr * const flow = (void *)(uintptr_t)TEGRA_FLOW_BASE; + const uint32_t req = 1 << 0; + const uint32_t sts = 1 << 1; + uint32_t reg; + struct mono_time t1, t2; + + printk(BIOS_DEBUG, "Requesting RAM repair.\n"); + + reg = read32(&flow->ram_repair); + reg |= req; + write32(reg, &flow->ram_repair); + + timer_monotonic_get(&t1); + while ((read32(&flow->ram_repair) & sts) != sts); + timer_monotonic_get(&t2); + + printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n", + mono_time_diff_microseconds(&t1, &t2)); +} + +void ccplex_cpu_prepare(void) +{ + enable_cpu_clocks(); + enable_cpu_power_partitions(); + + mainboard_configure_pmc(); + mainboard_enable_vdd_cpu(); + + request_ram_repair(); +} + +static void start_cpu0(void) +{ + struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS; + + /* Clear fast CPU partition reset. */ + write32(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr); + + /* Clear reset of CPU0 components. */ + write32(CRC_RST_CPUG_CLR_CPU0 | + CRC_RST_CPUG_CLR_DBG0 | + CRC_RST_CPUG_CLR_CORE0 | + CRC_RST_CPUG_CLR_CX0 | + CRC_RST_CPUG_CLR_L2 | + CRC_RST_CPUG_CLR_PDBG, &clk_rst->rst_cpug_cmplx_clr); +} + +/* + * The Denver cores come up in aarch32 mode. In order to transition to + * 64-bit mode a write to the RMR (reset mangement register) with the + * AA64 bit (0) set while setting RR (reset request bit 1). + */ +static const uint32_t aarch32to64[] = { + 0xe3a00003, /* mov r0, #3 */ + 0xee0c0f50, /* mcr 15, 0, r0, cr12, cr0, {2} */ +}; + +static void load_aarch64_trampoline(void *addr) +{ + const size_t trampoline_size = sizeof(aarch32to64); + const void * const trampoline = &aarch32to64[0]; + + /* Copy trampoline into ram. */ + memcpy(addr, trampoline, trampoline_size); +} + +void ccplex_cpu_start(void *entry_addr) +{ + struct tegra_pmc_regs * const pmc = PMC_REGS; + void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR; + void *trampoline; + uint32_t entry_point; + + /* + * Just place the trampoline at the MTS_LOAD_ADDRESS. This assumes + * the program to run doesn't overlap this address. + */ + const uint32_t trampoline_addr = MTS_LOAD_ADDRESS; + trampoline = (void *)(uintptr_t)trampoline_addr; + + /* The arm entry points have bit 0 set if thumb code. Mask that off. */ + entry_point = (uint32_t)(uintptr_t)entry_addr; + + load_aarch64_trampoline(trampoline); + + /* Warm reset vector is pulled from the PMC scratch registers. */ + write32(entry_point, &pmc->secure_scratch34); + write32(0, &pmc->secure_scratch35); + + printk(BIOS_DEBUG, "Starting CPU0 @ %p trampolining to %08x.\n", + trampoline, entry_point); + + /* + * The Denver cores start in 32-bit mode. Therefore a trampoline + * is needed to get into 64-bit mode. Point the cold reset vector + * to the trampoline location. + */ + write32(trampoline_addr, evp_cpu_reset_vector); + + start_cpu0(); +} diff --git a/src/soc/nvidia/tegra132/ccplex.h b/src/soc/nvidia/tegra132/ccplex.h index 6b9699cded..c3f8a04534 100644 --- a/src/soc/nvidia/tegra132/ccplex.h +++ b/src/soc/nvidia/tegra132/ccplex.h @@ -22,7 +22,13 @@ #define MTS_LOAD_ADDRESS 0x82000000 +/* Prepare the clocks and rails to start the cpu. */ +void ccplex_cpu_prepare(void); + /* Loads the MTS microcode. Return 0 on success, < 0 on error. */ int ccplex_load_mts(void); +/* Start cpu0 and have it start executing at entry_addr */ +void ccplex_cpu_start(void *entry_addr); + #endif /* __SOC_NVIDIA_TEGRA132_CCPLEX_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h new file mode 100644 index 0000000000..f9eac26e0d --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/romstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ +#define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ + +void mainboard_configure_pmc(void); +void mainboard_enable_vdd_cpu(void); + +#endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/power.c b/src/soc/nvidia/tegra132/power.c new file mode 100644 index 0000000000..5c7cc05ef4 --- /dev/null +++ b/src/soc/nvidia/tegra132/power.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/addressmap.h> + +#include "pmc.h" +#include "power.h" + +static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; + +static int partition_powered(int id) +{ + return read32(&pmc->pwrgate_status) & (0x1 << id); +} + +void power_ungate_partition(uint32_t id) +{ + printk(BIOS_INFO, "Ungating power partition %d.\n", id); + + if (!partition_powered(id)) { + uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle); + pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); + pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); + pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; + write32(pwrgate_toggle, &pmc->pwrgate_toggle); + + /* Wait for the request to be accepted. */ + while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) + ; + printk(BIOS_DEBUG, "Power gate toggle request accepted.\n"); + + /* Wait for the partition to be powered. */ + while (!partition_powered(id)) + ; + } + + printk(BIOS_INFO, "Ungated power partition %d.\n", id); +} diff --git a/src/soc/nvidia/tegra132/power.h b/src/soc/nvidia/tegra132/power.h index 9283b5583a..b36f91f15f 100644 --- a/src/soc/nvidia/tegra132/power.h +++ b/src/soc/nvidia/tegra132/power.h @@ -20,10 +20,8 @@ #ifndef __SOC_NVIDIA_TEGRA132_POWER_H__ #define __SOC_NVIDIA_TEGRA132_POWER_H__ -// This function does not enable the external power to the rail, it enables -// the rail itself internal to the SOC. -void power_enable_cpu_rail(void); +#include "pmc.h" -void power_ungate_cpu(void); +void power_ungate_partition(uint32_t id); #endif /* __SOC_NVIDIA_TEGRA132_POWER_H__ */ diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index 6d51403d04..1d6acca5d0 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -39,12 +39,16 @@ void romstage(void) sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); + ccplex_cpu_prepare(); + printk(BIOS_INFO, "T132 romstage: cpu prepare done\n"); + ccplex_load_mts(); printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); - while (1); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage"); - stage_exit(entry); + + ccplex_cpu_start(entry); + + while (1); } |