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-rw-r--r--src/soc/amd/stoneyridge/Kconfig6
-rw-r--r--src/soc/amd/stoneyridge/Makefile.inc3
-rw-r--r--src/soc/amd/stoneyridge/tsc_freq.c49
3 files changed, 56 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 6584fbb713..b431642fbe 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -34,12 +34,14 @@ config CPU_SPECIFIC_OPTIONS
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
- select LAPIC_MONOTONIC_TIMER
+ select UDELAY_TSC
+ select HAVE_MONOTONIC_TIMER
+ select TSC_MONOTONIC_TIMER
+ select TSC_CONSTANT_RATE
select SPI_FLASH if HAVE_ACPI_RESUME
select TSC_SYNC_LFENCE
select SOC_AMD_COMMON
select SOC_AMD_PI
- select UDELAY_LAPIC
config UDELAY_LAPIC_FIXED_FSB
int
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index d164769d82..97d402e0a2 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -46,6 +46,7 @@ romstage-y += smbus.c
romstage-y += smbus_spd.c
romstage-y += ramtop.c
romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
+romstage-y += tsc_freq.c
ramstage-y += chip.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
@@ -68,9 +69,11 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
ramstage-y += usb.c
+ramstage-y += tsc_freq.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge
CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include
diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c
new file mode 100644
index 0000000000..1f48306afe
--- /dev/null
+++ b/src/soc/amd/stoneyridge/tsc_freq.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2017 Advanced Micro Devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/amd/amdfam15.h>
+#include <console/console.h>
+#include <soc/pci_devs.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr;
+ uint8_t cpufid;
+ uint8_t cpudid;
+ uint8_t boost_states;
+
+ /*
+ * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for
+ * MSR0000_0010. The TSC increments at the P0 frequency. According
+ * to the "Software P-state Numbering" section, P0 is the highest
+ * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
+ */
+ boost_states = (pci_read_config32(DEV_D18F4, CORE_PERF_BOOST_CTRL)
+ >> 2) & 0x7;
+
+ msr = rdmsr(PSTATE_0_MSR + boost_states);
+ if (!(msr.hi & 0x80000000))
+ die("Unknown error: cannot determine P-state 0\n");
+
+ cpufid = (msr.lo & 0x3f);
+ cpudid = (msr.lo & 0x1c0) >> 6;
+
+ return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+}