diff options
Diffstat (limited to 'src/soc')
27 files changed, 144 insertions, 122 deletions
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index ff5dc87f78..e00ae917a5 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -70,70 +70,91 @@ void PRE_SRX(void) uint32_t readvalue = 0; // Disable low power receivers: bit 0 of the byte lane STATIC_PAD_CTL register - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); - reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, + (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); // Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1) - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); - reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, + (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); // Byte lane 0 power up - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, + (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f)); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, + (readvalue & 0xffff800f)); - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, + (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); // Byte lane 1 power up - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, + (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f)); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, + (readvalue & 0xffff800f)); - readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); + readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); + reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, + (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); // Turn on PHY_CONTROL AUTO_OEB C not required // Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a printk(BIOS_INFO, "\n....PLL power up.\n"); - reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN))); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, + (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & + ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN))); // PLL out of reset - reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET))); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, + (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & + ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET))); printk(BIOS_INFO, "\n....poll lock..\n"); // Poll lock readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS); - while ( ( readvalue & 0x1) == 0x0 ) + while ((readvalue & 0x1) == 0x0) { printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_PLL_STATUS = %8x..\n",readvalue); readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS); } printk(BIOS_INFO, "\n....after while..\n"); - reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV))); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, + (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & + ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV))); printk(BIOS_INFO, "\n....remove hold..\n"); // Remove hold - reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD))); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, + (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & + ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD))); printk(BIOS_INFO, "\n....restore dac..\n"); // Restore DAC - reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL, + (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); printk(BIOS_INFO, "\n....set iddq bit..\n"); // Set the iddq bit in the idle control register and select all outputs except cke and rst in the idee select registers. // Do NOT assert any other bits in the idle control register. (This step can be done during init on power up.) - reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ))); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, + (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & + ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ))); printk(BIOS_INFO, "\n....idle pad enable 0..\n"); reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, 0x0); reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, 0x0); printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL..\n"); - reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE))); + reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, + (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & + ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE))); } #endif @@ -143,7 +164,7 @@ void iproc_ddr_ovrd_ecc_lane(void) { uint32_t val; -#define SET_OVR_STEP(v) ( 0x30000 | ( (v) & 0x3F ) ) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ +#define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN); val = SET_OVR_STEP(val & 0xff); @@ -441,27 +462,27 @@ void ddr_phy_wl_regs_ovrd(unsigned int * tblptr) /*DDR_SHMOO_RELATED_CHANGE*/ #ifdef CONFIG_RUN_DDR_SHMOO -int ReWriteModeRegisters( void ) +int ReWriteModeRegisters(void) { int nRet = 0; int j = 100; - reg32_clear_bits( (volatile uint32_t *)DDR_DENALI_CTL_89 , 1 << 18 ); + reg32_clear_bits((volatile uint32_t *)DDR_DENALI_CTL_89, 1 << 18); /* Set mode register for MR0, MR1, MR2 and MR3 write for all chip selects */ - reg32_write( (volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25) ); + reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); /* Trigger Mode Register Write(MRW) sequence */ - reg32_set_bits( (volatile uint32_t *)DDR_DENALI_CTL_43 , 1 << 25 ); + reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_43, 1 << 25); do { - if ( reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) { + if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { break; } --j; - } while ( j ); + } while (j); - if ( j == 0 && (reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) == 0 ) { + if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { printk(BIOS_ERR, "Error: DRAM mode registers write failed\n"); nRet = 1; }; @@ -975,25 +996,24 @@ static int try_restore_shmoo(void) ) { val |= (1 << 17); /* Force Override */ } - // printk(BIOS_INFO, "Writing 0x%x to 0x%x\n",val,reg); - reg32_write(reg,val); + // printk(BIOS_INFO, "Writing 0x%x to 0x%x\n",val,reg); + reg32_write(reg, val); - reg32_read(reg); /* Dummy read back */ - } - printk(BIOS_INFO, "done\n"); - - /* Perform memory test to see if the parameters work */ - if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0 ) { - printk(BIOS_INFO, "Running simple memory test ..... "); - i = simple_memory_test( - (void *)CONFIG_SHMOO_REUSE_MEMTEST_START, - CONFIG_SHMOO_REUSE_MEMTEST_LENGTH); - if (i) { - printk(BIOS_ERR, "failed!\n"); - return 1; - } - printk(BIOS_INFO, "OK\n"); - } + reg32_read(reg); /* Dummy read back */ + } + printk(BIOS_INFO, "done\n"); + + /* Perform memory test to see if the parameters work */ + if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { + printk(BIOS_INFO, "Running simple memory test ..... "); + i = simple_memory_test((void *)CONFIG_SHMOO_REUSE_MEMTEST_START, + CONFIG_SHMOO_REUSE_MEMTEST_LENGTH); + if (i) { + printk(BIOS_ERR, "failed!\n"); + return 1; + } + printk(BIOS_INFO, "OK\n"); + } return 0; } @@ -1116,9 +1136,11 @@ static int clear_ddr(uint32_t offset, uint32_t size) unsigned long start; unsigned int i, val; - reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1); + reg32_write((uint32_t *)DDR_BistConfig, + reg32_read((uint32_t *)DDR_BistConfig) & ~0x1); - for ( i = 0; i < 1000; i++); + for (i = 0; i < 1000; i++) + ; #if !defined(CONFIG_IPROC_P7) reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF); @@ -1377,10 +1399,10 @@ void ddr_init2(void) /* Wait for DDR PHY up */ for (i=0; i < 0x19000; i++) { val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); - if ( val != 0) { - printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); + if (val != 0) { + printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); break; /* DDR PHY is up */ - } + } } if (i == 0x19000) { @@ -1484,7 +1506,7 @@ void ddr_init2(void) /* Enable auto self-refresh */ reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57, 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | - 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R); reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58, DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R); @@ -1495,9 +1517,9 @@ void ddr_init2(void) /* Disable auto-self refresh */ reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57, 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | - 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R); reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58, - 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R ); + 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R); #endif /* Start the DDR */ @@ -1598,7 +1620,7 @@ void ddr_init2(void) /* SRX */ if (skip_shmoo) { - // Enter Self refresh (dummy) , to keep Denali happy + // Enter Self refresh (dummy), to keep Denali happy reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x0a050505); __udelay(200); diff --git a/src/soc/broadcom/cygnus/phy_reg_access.c b/src/soc/broadcom/cygnus/phy_reg_access.c index eb48133656..ea82dde4df 100644 --- a/src/soc/broadcom/cygnus/phy_reg_access.c +++ b/src/soc/broadcom/cygnus/phy_reg_access.c @@ -15,17 +15,17 @@ uint32 REGRD (uint32 address) { - volatile unsigned long data; + volatile unsigned long data; - data = (* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))); - //printf("REGRD %08X=%08X\n", address, data); - return data; + data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); + //printf("REGRD %08X=%08X\n", address, data); + return data; } uint32 REGWR (uint32 address, uint32 data) { - ((* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); - //printf("REGWR %08X=%08X\n", address, data); -// return SOC_E_NONE; - return 0; + ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); + //printf("REGWR %08X=%08X\n", address, data); + // return SOC_E_NONE; + return 0; } diff --git a/src/soc/broadcom/cygnus/usb.c b/src/soc/broadcom/cygnus/usb.c index d95efd1a87..5b93604412 100644 --- a/src/soc/broadcom/cygnus/usb.c +++ b/src/soc/broadcom/cygnus/usb.c @@ -47,7 +47,7 @@ struct bcm_phy_instance { struct phy *generic_phy; int port; - int host_mode; /* 1 - Host , 0 - device */ + int host_mode; /* 1 - Host, 0 - device */ int power; /* 1 -powered_on 0 -powered off */ struct regulator *vbus_supply; }; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 7208e88d43..3e03ca5d98 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -229,7 +229,7 @@ static void byt_pcie_enable(struct device *dev) static void byt_pciexp_scan_bridge(struct device *dev) { static const struct reg_script wait_for_link_active[] = { - REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000), + REG_PCI_POLL32(LCTL, (1 << 29), (1 << 29), 50000), REG_SCRIPT_END, }; diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 20a066450d..6cddf766c3 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -221,7 +221,7 @@ E(CCU, 0x28, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en -E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en +E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 4d135390f6..ccd6c9fe41 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -24,7 +24,7 @@ static void pci_domain_set_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); assign_resources(dev->link_list); } @@ -49,7 +49,7 @@ static struct device_operations cpu_bus_ops = { static void enable_dev(struct device *dev) { - printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n", + printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", __FILE__, __func__, dev_name(dev), dev->path.type); printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", @@ -384,7 +384,7 @@ struct chip_operations soc_intel_braswell_ops = { static void pci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { - printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n", __FILE__, __func__, dev_name(dev), vendor, device); if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 27903e86e0..195dba4aea 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -47,7 +47,7 @@ static const struct reg_script core_msr_script[] = { static void soc_core_init(struct device *cpu) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(cpu)); printk(BIOS_DEBUG, "Init Braswell core.\n"); @@ -219,7 +219,7 @@ void soc_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (mp_init_with_smm(cpu_bus, &mp_ops)) diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 44116a8877..238f8db4b8 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -36,7 +36,7 @@ static void emmc_init(struct device *dev) { struct soc_intel_braswell_config *config = dev->chip_info; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index b3295316a6..895d2ee7da 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -49,7 +49,7 @@ static inline void gfx_run_script(struct device *dev, static void gfx_pre_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); @@ -57,7 +57,7 @@ static void gfx_pre_vbios_init(struct device *dev) static void gfx_post_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); @@ -65,7 +65,7 @@ static void gfx_post_vbios_init(struct device *dev) static void gfx_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Pre VBIOS Init */ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 7c9f30637a..6338878a1e 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -153,7 +153,7 @@ static void lpe_init(struct device *dev) { struct soc_intel_braswell_config *config = dev->chip_info; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); lpe_stash_firmware_info(dev); diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index aac953ba1f..60ff49f709 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -143,7 +143,7 @@ static void lpss_init(struct device *dev) struct soc_intel_braswell_config *config = dev->chip_info; int iosf_reg, nvs_index; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_SPEW, "%s - %s\n", get_pci_class_name(dev), diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 1a127f4190..efd891a7c8 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -41,7 +41,7 @@ static inline int is_first_port(struct device *dev) static void pcie_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); } @@ -56,7 +56,7 @@ static void check_port_enabled(struct device *dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); switch (root_port_offset(dev)) { @@ -99,7 +99,7 @@ static void check_device_present(struct device *dev) static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -137,7 +137,7 @@ static void check_device_present(struct device *dev) static void pcie_enable(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (is_first_port(dev)) { struct soc_intel_braswell_config *config = dev->chip_info; @@ -162,7 +162,7 @@ static void pcie_enable(struct device *dev) static void pcie_root_set_subsystem(struct device *dev, unsigned int vid, unsigned int did) { - printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n", __FILE__, __func__, dev_name(dev), vid, did); uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index 8052b29e08..250764153f 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -30,7 +30,7 @@ typedef struct soc_intel_braswell_config config_t; static void sata_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); } diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 122c67ea39..17fc685b3c 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -29,7 +29,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) struct resource *bar; global_nvs_t *gnvs; - printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n", __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index); /* Find ACPI NVS to update BARs */ diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 97c39b3254..1775ce74be 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -35,7 +35,7 @@ static void sd_init(struct device *dev) { struct soc_intel_braswell_config *config = dev->chip_info; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (config == NULL) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 14b412a03f..ca87d63aa0 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -55,14 +55,14 @@ static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { - printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n", __FILE__, __func__, dev_name(dev), addr, size); mmio_resource(dev, i, addr >> 10, size >> 10); } static void sc_add_mmio_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -102,7 +102,7 @@ static void sc_add_io_resource(struct device *dev, int base, int size, { struct resource *res; - printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x, 0x%08x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x, 0x%08x)\n", __FILE__, __func__, dev_name(dev), base, size, index); if (io_range_in_default(base, size)) @@ -118,7 +118,7 @@ static void sc_add_io_resources(struct device *dev) { struct resource *res; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Add the default claimed IO range for the LPC device. */ @@ -136,7 +136,7 @@ static void sc_add_io_resources(struct device *dev) static void sc_read_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Get the normal PCI resources of this device. */ @@ -165,7 +165,7 @@ static void sc_init(struct device *dev) const struct soc_irq_route *ir = &global_soc_irq_route; struct soc_intel_braswell_config *config = dev->chip_info; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Set up the PIRQ PIC routing based on static config. */ @@ -206,7 +206,7 @@ static void sc_disable_devfn(struct device *dev) uint32_t mask = 0; uint32_t mask2 = 0; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); #define SET_DIS_MASK(name_) \ @@ -292,7 +292,7 @@ static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; - printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%08x)\n", __FILE__, __func__, dev_name(dev), offset); printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); reg8 = pci_read_config8(dev, offset + 4); @@ -309,7 +309,7 @@ static void hda_work_around(struct device *dev) { void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Need to set magic register 0x43 to 0xd7 in config space. */ @@ -331,7 +331,7 @@ static int place_device_in_d3hot(struct device *dev) { unsigned int offset; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* @@ -410,7 +410,7 @@ void southcluster_enable_dev(struct device *dev) { uint32_t reg32; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); @@ -461,7 +461,7 @@ static const struct pci_driver southcluster __pci_driver = { int __weak mainboard_get_spi_config(struct spi_config *cfg) { - printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", + printk(BIOS_SPEW, "%s/%s (0x%p)\n", __FILE__, __func__, (void *)cfg); return -1; } @@ -475,7 +475,7 @@ static void finalize_chipset(void *unused) uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct spi_config cfg; - printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", + printk(BIOS_SPEW, "%s/%s (0x%p)\n", __FILE__, __func__, unused); /* Set the lock enable on the BIOS control register. */ diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 6f0049f9d0..8ce0a1d523 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -37,8 +37,8 @@ static void check_for_warm_reset(void) * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set. * If either is true, then this is a warm reset so execute a Hard Reset */ - if ( (inb(0xcf9) == 0x04) || - (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE) ) { + if ((inb(0xcf9) == 0x04) || + (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE)) { outb(0x00, 0xcf9); outb(0x06, 0xcf9); } diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c5863f459f..13bc883781 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -314,7 +314,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, if (prev_sleep_state == ACPI_S3) { /* S3 resume */ - if ( pFspInitParams->NvsBufferPtr == NULL) { + if (pFspInitParams->NvsBufferPtr == NULL) { /* If waking from S3 and no cache then. */ printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); @@ -322,7 +322,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); /* Reboot */ - printk(BIOS_WARNING,"Rebooting..\n" ); + printk(BIOS_WARNING, "Rebooting..\n" ); system_reset(); /* Should not reach here.. */ die("Reboot System\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 9f22b25a5d..f909121eb2 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -158,7 +158,7 @@ static void mc_add_dram_resources(struct device *dev) (bmbound - fsp_mem_base) >> 10); if (highmem_size) { - ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10 ); + ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); } printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", highmem_size >> 20); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 7a25bfe8a7..df2eb9c951 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -589,9 +589,9 @@ u8 dramk_calcu_best_dly(u8 bit, struct dqs_perbit_dly *p, u8 *p_max_byte) } } else if (hold < setup) { - /* like this: (hold time != 0 )*/ + /* like this: (hold time != 0)*/ /* xxxoooooooooooooooooo|ooooooooxxxxxxxxxxxxxxxxx */ - /* like this: (hold time == 0 ) */ + /* like this: (hold time == 0) */ /* xxxoooooooooooooooxxx|xxxxxxxxxxxxxxxxxxxxxxxxx */ p->best_dqsdly = 0; @@ -972,7 +972,7 @@ void perbit_window_cal(u32 channel, u8 type) dqdqs_perbit_dly[i].best_last_dqsdly_pass = -2; } - /* 1. delay DQ ,find the pass widnow (left boundary) + /* 1. delay DQ,find the pass widnow (left boundary) * 2. delay DQS find the pass window (right boundary) * 3. find the best DQ / DQS to satify the middle value * of the overall pass window per bit @@ -1121,7 +1121,7 @@ void perbit_window_cal(u32 channel, u8 type) dramc_dbg_msg("DQ Delay :\n"); for (i = 0; i < DATA_WIDTH_32BIT; i++) { dramc_dbg_msg("DQ%d = %d ", i, dqdqs_perbit_dly[i].best_dqdly); - if ( ((i + 1) % 4) == 0) + if (((i + 1) % 4) == 0) dramc_dbg_msg("\n"); } diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index c021303a4d..872ed6cf11 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -138,19 +138,19 @@ size_t sdram_size(void) if (value & CONA_DUAL_CH_EN) bit_counter++; - /* check if 32bit , 32 = 2^5*/ + /* check if 32bit, 32 = 2^5*/ if (value & CONA_32BIT_EN) bit_counter += 5; else bit_counter += 4; /* check column address */ - /* 00 is 9 bits, 01 is 10 bits , 10 is 11 bits */ + /* 00 is 9 bits, 01 is 10 bits, 10 is 11 bits */ bit_counter += ((value & COL_ADDR_BITS_MASK) >> COL_ADDR_BITS_SHIFT) + 9; /* check if row address */ - /*00 is 13 bits , 01 is 14 bits , 10 is 15bits , 11 is 16 bits */ + /*00 is 13 bits, 01 is 14 bits, 10 is 15bits, 11 is 16 bits */ bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) + 13; diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index 79ed316cb5..31c77f5240 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -58,7 +58,7 @@ static void gpio_set_duty(enum external_power ext_power) } /* other R/TDSEL */ - /* msdc2_ctrl5 , bit[3:0] = b`1010 */ + /* msdc2_ctrl5, bit[3:0] = b`1010 */ write16(&mtk_gpio->msdc2_ctrl5.set, 0xA); write16(&mtk_gpio->msdc2_ctrl5.rst, 0x5); } diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index 536ad31804..5cc5889f87 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -44,9 +44,9 @@ void sdram_lp0_save_params(const struct sdram_params *sdram) #define pack(src, src_bits, dst, dst_bits) { \ _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ - (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \ + (0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \ _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \ - (0 ? dst_bits), "src and dst byte range lengths differ" ); \ + (0 ? dst_bits), "src and dst byte range lengths differ"); \ u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ dst &= ~(mask << (0 ? dst_bits)); \ dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index c3a4dd407d..9eaf5f0550 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -32,9 +32,9 @@ void sdram_lp0_save_params(const struct sdram_params *sdram) #define pack(src, src_bits, dst, dst_bits) { \ _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ - (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \ + (0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \ _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \ - (0 ? dst_bits), "src and dst byte range lengths differ" ); \ + (0 ? dst_bits), "src and dst byte range lengths differ"); \ u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ dst &= ~(mask << (0 ? dst_bits)); \ dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 41056f8937..662116ecb5 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -47,7 +47,7 @@ void *gpio_grf_reg(gpio_t gpio) { if (is_pmu_gpio(gpio)) return &rk3288_pmu->gpio0pull[gpio.bank]; - /* There is one pmu gpio, gpio0 , so " - 1" */ + /* There is one pmu gpio, gpio0, so " - 1" */ return &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank]; } diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index 63e30f6749..a6cc3c78b9 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -617,7 +617,7 @@ int clock_epll_set_rate(unsigned long rate) epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; /* - * Required period ( in cycles) to generate a stable clock output. + * Required period (in cycles) to generate a stable clock output. * The maximum clock time can be up to 3000 * PDIV cycles of PLLs * frequency input (as per spec) */ diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 3c4bb04794..04125d9cb1 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -582,7 +582,7 @@ int clock_epll_set_rate(unsigned long rate) epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; /* - * Required period ( in cycles) to generate a stable clock output. + * Required period (in cycles) to generate a stable clock output. * The maximum clock time can be up to 3000 * PDIV cycles of PLLs * frequency input (as per spec) */ |