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-rw-r--r--src/soc/intel/broadwell/pcie.c1
-rw-r--r--src/soc/intel/common/block/pcie/pcie.c5
2 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 14dcd3f556..00a8595eeb 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -587,7 +587,6 @@ static void pch_pcie_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_PARITY;
- reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Clear errors in status registers */
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index f36366a754..ada380e493 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -24,9 +24,8 @@ static void pch_pcie_init(struct device *dev)
/* Set Cache Line Size to 0x10 */
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
- /* disable parity error response, enable ISA */
- pci_update_config16(dev, PCI_BRIDGE_CONTROL,
- ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
+ /* disable parity error response */
+ pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
if (CONFIG(PCIE_DEBUG_INFO)) {
printk(BIOS_SPEW, " MBL = 0x%08x\n",