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-rw-r--r--src/soc/mediatek/mt8173/include/soc/memlayout.ld3
-rw-r--r--src/soc/mediatek/mt8183/include/soc/memlayout.ld3
-rw-r--r--src/soc/nvidia/tegra124/include/soc/memlayout.ld3
-rw-r--r--src/soc/nvidia/tegra210/include/soc/memlayout.ld3
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld3
-rw-r--r--src/soc/qualcomm/ipq806x/include/soc/memlayout.ld3
-rw-r--r--src/soc/qualcomm/qcs405/include/soc/memlayout.ld3
-rw-r--r--src/soc/qualcomm/sc7180/include/soc/memlayout.ld1
-rw-r--r--src/soc/rockchip/rk3399/include/soc/memlayout.ld3
-rw-r--r--src/soc/samsung/exynos5250/include/soc/memlayout.ld3
-rw-r--r--src/soc/samsung/exynos5420/include/soc/memlayout.ld3
11 files changed, 21 insertions, 10 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld
index adda86e11b..2358c3940c 100644
--- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld
@@ -40,7 +40,8 @@ SECTIONS
SRAM_START(0x00100000)
VBOOT2_WORK(0x00100000, 12K)
VBOOT2_TPM_LOG(0x00103000, 2K)
- PRERAM_CBMEM_CONSOLE(0x00103800, 14K)
+ FMAP_CACHE(0x00103800, 2K)
+ PRERAM_CBMEM_CONSOLE(0x00104000, 12K)
WATCHDOG_TOMBSTONE(0x00107000, 4)
PRERAM_CBFS_CACHE(0x00107004, 16K - 4)
TIMESTAMP(0x0010B000, 4K)
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
index 82e404f790..a8f464a3d8 100644
--- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
@@ -34,7 +34,8 @@ SECTIONS
VBOOT2_TPM_LOG(0x00103000, 2K)
PRERAM_CBMEM_CONSOLE(0x00103800, 14K)
WATCHDOG_TOMBSTONE(0x00107000, 4)
- PRERAM_CBFS_CACHE(0x00107004, 48K - 4)
+ PRERAM_CBFS_CACHE(0x00107004, 46K - 4)
+ FMAP_CACHE(0x00112800, 2K)
TIMESTAMP(0x00113000, 4K)
STACK(0x00114000, 16K)
TTB(0x00118000, 28K)
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
index 7e2f9ec2af..7e2cc7ad58 100644
--- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld
@@ -28,7 +28,8 @@ SECTIONS
SRAM_START(0x40000000)
TTB(0x40000000, 16K + 32)
PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32)
- PRERAM_CBFS_CACHE(0x40005800, 16K)
+ FMAP_CACHE(0x40005800, 2K)
+ PRERAM_CBFS_CACHE(0x40006000, 14K)
VBOOT2_WORK(0x40009800, 12K)
VBOOT2_TPM_LOG(0x4000D800, 2K)
STACK(0x4000E000, 8K)
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld
index 1134da6111..b7268d114b 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld
@@ -29,7 +29,8 @@ SECTIONS
{
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 2K)
- PRERAM_CBFS_CACHE(0x40000800, 30K)
+ FMAP_CACHE(0x40000800, 2K)
+ PRERAM_CBFS_CACHE(0x40001000, 28K)
VBOOT2_WORK(0x40008000, 12K)
VBOOT2_TPM_LOG(0x4000B000, 2K)
#if ENV_ARM64
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
index f1a7bc59d2..6ff1018272 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
@@ -34,7 +34,8 @@ SECTIONS
/* This includes bootblock image, can be reused after bootblock starts */
/* UBER_SBL(0x0A0C0000, 48K) */
- PRERAM_CBFS_CACHE(0x0A0C0000, 93K)
+ PRERAM_CBFS_CACHE(0x0A0C0000, 92K)
+ FMAP_CACHE(0x0A0EF800, 2K)
TTB(0x0A0F0000, 16K)
TTB_SUBTABLES(0x0A0F4000, 4K)
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index 25db17587c..595d939d0b 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -38,7 +38,8 @@ SECTIONS
QCA_SHARED_RAM(2A03F000, 4K)
*/
STACK(0x2A040000, 16K)
- PRERAM_CBFS_CACHE(0x2A044000, 93K)
+ PRERAM_CBFS_CACHE(0x2A044000, 91K)
+ FMAP_CACHE(0x2A05B000, 2K)
TTB_SUBTABLES(0x2A05B800, 2K)
TTB(0x2A05C000, 16K)
SRAM_END(0x2A060000)
diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
index 68642d67a2..dd013b5e8f 100644
--- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
@@ -39,7 +39,8 @@ SECTIONS
TIMESTAMP(0x8C4F000, 1K)
PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
PRERAM_CBFS_CACHE(0x8C57400, 70K)
- REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100)
+ FMAP_CACHE(0x8C68C00, 2K)
+ REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100)
BSRAM_END(0x8D80000)
DRAM_START(0x80000000)
diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
index b2ee3b20a0..3f43419d14 100644
--- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
@@ -43,6 +43,7 @@ SECTIONS
REGION(ddr_training, 0x14850000, 8K, 4K)
REGION(qclib_serial_log, 0x14852000, 4K, 4K)
REGION(ddr_information, 0x14853000, 1K, 1K)
+ FMAP_CACHE(0x14853400, 2K)
REGION(dcb, 0x14870000, 16K, 4K)
REGION(pmic, 0x14874000, 44K, 4K)
REGION(limits_cfg, 0x1487F000, 4K, 4K)
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index 293057a091..4e46e2d764 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -33,7 +33,8 @@ SECTIONS
#if ENV_RAMSTAGE
REGION(bl31_sram, 0xFF8C0000, 64K, 1)
#else
- PRERAM_CBFS_CACHE(0xFF8C0000, 7K)
+ PRERAM_CBFS_CACHE(0xFF8C0000, 5K)
+ FMAP_CACHE(0xFF8C1400, 2K)
TIMESTAMP(0xFF8C1C00, 1K)
/* 0xFF8C2004 is the entry point address the masked ROM will jump to. */
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4)
diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
index 0bd319e45d..7e052f0f31 100644
--- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld
@@ -31,7 +31,8 @@ SECTIONS
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
- PRERAM_CBFS_CACHE(0x205C000, 78K)
+ PRERAM_CBFS_CACHE(0x205C000, 76K)
+ FMAP_CACHE(0x206F000, 2K)
VBOOT2_TPM_LOG(0x206F800, 2K)
VBOOT2_WORK(0x2070000, 12K)
STACK(0x2074000, 16K)
diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld
index bc5d0669da..ff781d2228 100644
--- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld
+++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld
@@ -32,7 +32,8 @@ SECTIONS
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
- PRERAM_CBFS_CACHE(0x205C000, 76K)
+ PRERAM_CBFS_CACHE(0x205C000, 74K)
+ FMAP_CACHE(0x206E800, 2K)
STACK(0x206F000, 16K)
/* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't
* seem to be implemented right now? */