diff options
Diffstat (limited to 'src/southbridge/amd/cimx')
-rw-r--r-- | src/southbridge/amd/cimx/sb700/bootblock.c | 2 | ||||
-rw-r--r-- | src/southbridge/amd/cimx/sb800/bootblock.c | 6 | ||||
-rw-r--r-- | src/southbridge/amd/cimx/sb900/bootblock.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 1027659d5c..4ddfb92ccf 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -24,7 +24,7 @@ static void sb700_enable_rom(void) { u32 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB700 LPC Bridge 0:20:3:44h. diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 4fd2739442..188ba291f9 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -23,7 +23,7 @@ static void enable_rom(void) { u16 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB800 LPC Bridge 0:20:3:44h. @@ -57,7 +57,7 @@ static void enable_rom(void) static void enable_prefetch(void) { u32 dword; - device_t dev = PCI_DEV(0, 0x14, 0x03); + pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* Enable PrefetchEnSPIFromHost */ dword = pci_io_read_config32(dev, 0xb8); @@ -67,7 +67,7 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { u32 dword; - device_t dev = PCI_DEV(0, 0x14, 0x03); + pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index 9108a8bb75..561904e942 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -23,7 +23,7 @@ static void sb900_enable_rom(void) { u32 word; u32 dword; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB900 LPC Bridge 0:20:3:44h. |