diff options
Diffstat (limited to 'src/southbridge/amd/cs5530')
| -rw-r--r-- | src/southbridge/amd/cs5530/Config.lb | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5530/bitmap.c | 304 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5530/cs5530_vga.c | 458 |
3 files changed, 763 insertions, 0 deletions
diff --git a/src/southbridge/amd/cs5530/Config.lb b/src/southbridge/amd/cs5530/Config.lb index e50cde5f5a..5a98ee62a2 100644 --- a/src/southbridge/amd/cs5530/Config.lb +++ b/src/southbridge/amd/cs5530/Config.lb @@ -22,3 +22,4 @@ config chip.h driver cs5530.o driver cs5530_isa.o driver cs5530_ide.o +driver cs5530_vga.o diff --git a/src/southbridge/amd/cs5530/bitmap.c b/src/southbridge/amd/cs5530/bitmap.c new file mode 100644 index 0000000000..0e5e02c572 --- /dev/null +++ b/src/southbridge/amd/cs5530/bitmap.c @@ -0,0 +1,304 @@ +/* do not edit +This is an image of size 51 x 60 with 234 colours */ +static const int width=51; +static const int height=60; +static const int colours=234; +static const unsigned long colour_map[234] = { +0x00000000, /* 0 */ +0x00000001, /* 1 */ +0x00000020, /* 2 */ +0x00000021, /* 3 */ +0x00000040, /* 4 */ +0x00000800, /* 5 */ +0x00000821, /* 6 */ +0x00000840, /* 7 */ +0x00000841, /* 8 */ +0x00000861, /* 9 */ +0x00001040, /* 10 */ +0x00001081, /* 11 */ +0x00001082, /* 12 */ +0x00001083, /* 13 */ +0x000010A2, /* 14 */ +0x00001881, /* 15 */ +0x000018C3, /* 16 */ +0x000018E3, /* 17 */ +0x000020A0, /* 18 */ +0x000020E4, /* 19 */ +0x00002103, /* 20 */ +0x00002104, /* 21 */ +0x00002124, /* 22 */ +0x00002921, /* 23 */ +0x00002945, /* 24 */ +0x00002946, /* 25 */ +0x00002965, /* 26 */ +0x00002966, /* 27 */ +0x00003186, /* 28 */ +0x000031A6, /* 29 */ +0x00003942, /* 30 */ +0x00003982, /* 31 */ +0x000039A7, /* 32 */ +0x000039C7, /* 33 */ +0x000039E7, /* 34 */ +0x000039E8, /* 35 */ +0x000041A2, /* 36 */ +0x000041C2, /* 37 */ +0x000041E7, /* 38 */ +0x00004207, /* 39 */ +0x00004208, /* 40 */ +0x00004228, /* 41 */ +0x00004229, /* 42 */ +0x000049E3, /* 43 */ +0x000049E5, /* 44 */ +0x00004A46, /* 45 */ +0x00004A47, /* 46 */ +0x00004A48, /* 47 */ +0x00004A49, /* 48 */ +0x00004A69, /* 49 */ +0x00004A8A, /* 50 */ +0x00005228, /* 51 */ +0x00005247, /* 52 */ +0x00005287, /* 53 */ +0x0000528A, /* 54 */ +0x000052AA, /* 55 */ +0x00005A21, /* 56 */ +0x00005A43, /* 57 */ +0x00005A63, /* 58 */ +0x00005AA9, /* 59 */ +0x00005AAA, /* 60 */ +0x00005ACA, /* 61 */ +0x00005ACB, /* 62 */ +0x00005AEB, /* 63 */ +0x00006222, /* 64 */ +0x00006261, /* 65 */ +0x000062A8, /* 66 */ +0x000062C7, /* 67 */ +0x000062E8, /* 68 */ +0x000062EB, /* 69 */ +0x000062EC, /* 70 */ +0x0000630B, /* 71 */ +0x0000630C, /* 72 */ +0x0000632C, /* 73 */ +0x00006A41, /* 74 */ +0x00006B05, /* 75 */ +0x00006B28, /* 76 */ +0x00006B29, /* 77 */ +0x00006B2D, /* 78 */ +0x00006B4D, /* 79 */ +0x00006B6D, /* 80 */ +0x00006B6E, /* 81 */ +0x00006B8D, /* 82 */ +0x000072A2, /* 83 */ +0x000072E2, /* 84 */ +0x000072E5, /* 85 */ +0x00007306, /* 86 */ +0x00007329, /* 87 */ +0x0000738E, /* 88 */ +0x000073AE, /* 89 */ +0x000073AF, /* 90 */ +0x000073CF, /* 91 */ +0x00007B28, /* 92 */ +0x00007B44, /* 93 */ +0x00007B48, /* 94 */ +0x00007B67, /* 95 */ +0x00007B69, /* 96 */ +0x00007BCE, /* 97 */ +0x00007BCF, /* 98 */ +0x00007BEF, /* 99 */ +0x00008323, /* 100 */ +0x00008345, /* 101 */ +0x000083AA, /* 102 */ +0x00008410, /* 103 */ +0x00008430, /* 104 */ +0x00008B02, /* 105 */ +0x00008B63, /* 106 */ +0x00008B83, /* 107 */ +0x00008B84, /* 108 */ +0x00008BA6, /* 109 */ +0x00008BC7, /* 110 */ +0x00008BEA, /* 111 */ +0x00008BEE, /* 112 */ +0x00008C51, /* 113 */ +0x00008C71, /* 114 */ +0x00009362, /* 115 */ +0x00009363, /* 116 */ +0x00009383, /* 117 */ +0x000093C5, /* 118 */ +0x000093C7, /* 119 */ +0x00009405, /* 120 */ +0x00009492, /* 121 */ +0x00009493, /* 122 */ +0x000094B2, /* 123 */ +0x00009B82, /* 124 */ +0x00009BC3, /* 125 */ +0x00009C2D, /* 126 */ +0x00009CB3, /* 127 */ +0x00009CD3, /* 128 */ +0x00009CF3, /* 129 */ +0x00009CF4, /* 130 */ +0x00009D14, /* 131 */ +0x0000A401, /* 132 */ +0x0000A403, /* 133 */ +0x0000A423, /* 134 */ +0x0000A44C, /* 135 */ +0x0000A489, /* 136 */ +0x0000A4F1, /* 137 */ +0x0000A514, /* 138 */ +0x0000A533, /* 139 */ +0x0000A534, /* 140 */ +0x0000ABE1, /* 141 */ +0x0000AC22, /* 142 */ +0x0000AC24, /* 143 */ +0x0000AC42, /* 144 */ +0x0000AC44, /* 145 */ +0x0000AC48, /* 146 */ +0x0000AC69, /* 147 */ +0x0000AC8A, /* 148 */ +0x0000ACEE, /* 149 */ +0x0000AD0A, /* 150 */ +0x0000AD2E, /* 151 */ +0x0000AD55, /* 152 */ +0x0000AD75, /* 153 */ +0x0000AD76, /* 154 */ +0x0000B423, /* 155 */ +0x0000B441, /* 156 */ +0x0000B444, /* 157 */ +0x0000B464, /* 158 */ +0x0000B484, /* 159 */ +0x0000B4A3, /* 160 */ +0x0000B4C4, /* 161 */ +0x0000B533, /* 162 */ +0x0000B596, /* 163 */ +0x0000B5B6, /* 164 */ +0x0000BC65, /* 165 */ +0x0000BC83, /* 166 */ +0x0000BC84, /* 167 */ +0x0000BCC9, /* 168 */ +0x0000BD03, /* 169 */ +0x0000BD2A, /* 170 */ +0x0000BD54, /* 171 */ +0x0000BD97, /* 172 */ +0x0000BDB5, /* 173 */ +0x0000BDD7, /* 174 */ +0x0000BDD8, /* 175 */ +0x0000BDF7, /* 176 */ +0x0000BE19, /* 177 */ +0x0000C4A2, /* 178 */ +0x0000C4C2, /* 179 */ +0x0000C4C3, /* 180 */ +0x0000C5CE, /* 181 */ +0x0000C5F9, /* 182 */ +0x0000C618, /* 183 */ +0x0000C61A, /* 184 */ +0x0000C638, /* 185 */ +0x0000CCE2, /* 186 */ +0x0000CD03, /* 187 */ +0x0000CD43, /* 188 */ +0x0000CD61, /* 189 */ +0x0000CD88, /* 190 */ +0x0000CE39, /* 191 */ +0x0000CE58, /* 192 */ +0x0000CE59, /* 193 */ +0x0000CE79, /* 194 */ +0x0000CE7A, /* 195 */ +0x0000CE7B, /* 196 */ +0x0000CE9A, /* 197 */ +0x0000D502, /* 198 */ +0x0000D522, /* 199 */ +0x0000D62C, /* 200 */ +0x0000D69A, /* 201 */ +0x0000D69B, /* 202 */ +0x0000D6BA, /* 203 */ +0x0000DD23, /* 204 */ +0x0000DD41, /* 205 */ +0x0000DD81, /* 206 */ +0x0000DDA1, /* 207 */ +0x0000DDA4, /* 208 */ +0x0000DE9C, /* 209 */ +0x0000DEDB, /* 210 */ +0x0000DEFB, /* 211 */ +0x0000DEFD, /* 212 */ +0x0000E5A2, /* 213 */ +0x0000E71C, /* 214 */ +0x0000E73C, /* 215 */ +0x0000EDC1, /* 216 */ +0x0000EF3E, /* 217 */ +0x0000EF5D, /* 218 */ +0x0000EF7D, /* 219 */ +0x0000EF7E, /* 220 */ +0x0000EF7F, /* 221 */ +0x0000F79D, /* 222 */ +0x0000F79E, /* 223 */ +0x0000F7BE, /* 224 */ +0x0000F7BF, /* 225 */ +0x0000F7DE, /* 226 */ +0x0000FFB8, /* 227 */ +0x0000FFBF, /* 228 */ +0x0000FFDD, /* 229 */ +0x0000FFDE, /* 230 */ +0x0000FFDF, /* 231 */ +0x0000FFFB, /* 232 */ +0x0000FFFF, /* 233 */ +}; + +static const unsigned char bitmap[3060] = { +0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE7,0xA4,0xD3,0xE9,0xDF,0xDF,0x8C,0xE7,0xE0,0xDF,0xB0,0xDB,0xE7,0xE0,0xE0,0xC2,0xE7,0xE7,0xE0,0xD3,0xE9,0xE9,0xE0,0xDF,0xDF,0xE7,0xE7,0xD6,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9, +0xE9,0xE9,0xE9,0xE9,0xE0,0xDB,0xDA,0xDF,0xE9,0x67,0xA3,0xD7,0xDA,0xE9,0x71,0xD7,0xA3,0xE9,0xD6,0xD7,0xD2,0xD6,0xE9,0xC1,0xDF,0x68,0xE9,0xDA,0xE0,0x99,0xAE,0xE9,0xD7,0xB9,0xE9,0xA3,0xDF,0xE0,0xE7,0xE7,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9, +0xE9,0xE9,0xE9,0xD6,0x71,0x67,0x63,0x72,0xE9,0x31,0x4F,0x58,0x99,0xD6,0x1D,0x67,0x50,0xB7,0x67,0x36,0x4F,0x99,0xD6,0x28,0x49,0x3F,0xDB,0x71,0x48,0x48,0x80,0xDB,0x37,0x48,0xE9,0x8C,0x58,0x68,0xDA,0xDB,0xDF,0xE0,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9, +0xE9,0xE9,0xE9,0x79,0x63,0x63,0x58,0x29,0x7B,0x1A,0x28,0x30,0x30,0x63,0x0C,0x50,0x10,0x50,0x28,0x21,0x1D,0x31,0x62,0x11,0x36,0x10,0x68,0x30,0x30,0x16,0x3E,0x68,0x15,0x29,0x8C,0x3E,0x11,0x36,0x4F,0xC2,0xD7,0xDA,0xDF,0xE7,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9, +0xE9,0xE9,0xE7,0x62,0x62,0x63,0x63,0x22,0x37,0x16,0x28,0x36,0x1C,0x28,0x0C,0x49,0x15,0x29,0x16,0x21,0x1D,0x22,0x22,0x0C,0x31,0x11,0x29,0x15,0x21,0x15,0x22,0x22,0x10,0x22,0x48,0x1D,0x08,0x3E,0x29,0x3E,0xB9,0xD2,0xD7,0xDB,0xE0,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9, +0xE9,0xE9,0xDB,0x62,0x4F,0x4F,0x3F,0x30,0x21,0x15,0x28,0x31,0x22,0x1A,0x0C,0x50,0x18,0x1D,0x0E,0x29,0x1D,0x22,0x16,0x10,0x37,0x1D,0x1D,0x0C,0x28,0x1A,0x29,0x1A,0x18,0x21,0x21,0x16,0x0E,0x3E,0x29,0x30,0x48,0xB0,0xC9,0xD3,0xDB,0xE0,0xE7,0xE9,0xE9,0xE9,0xE9, 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+/* + * Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * + * Purpose: + * Activate the VGA feature in a Geode GX1 based system with one of five + * possible VESA modes: VGA, SVGA, XGA, 4:3 SXGA and 5:4 SXGA. Also it is + * prepared to display a splash screen. + */ +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <cpu/amd/gx1def.h> +#include <delay.h> + +#if CONFIG_GX1_VIDEO == 1 +/* + * Some register descriptions that are no listed in cpu/amd/gx1def.h + */ +#define CS5530_DOT_CLK_CONFIG 0x0024 +#define CS5530_DISPLAY_CONFIG 0x0004 + +#define DC_FB_ST_OFFSET 0x8310 /* framebuffer start offset */ +#define DC_CB_ST_OFFSET 0x8314 /* compression start offset */ +#define DC_CURS_ST_OFFSET 0x8318 /* cursor start offset */ +#define DC_VID_ST_OFFSET 0x8320 /* video start offset */ +#define DC_LINE_DELTA 0x8324 /* fb and cb skip counts */ +#define DC_BUF_SIZE 0x8328 /* fb and cb line size */ +#define DC_H_TIMING_1 0x8330 /* horizontal timing... */ +#define DC_H_TIMING_2 0x8334 +#define DC_H_TIMING_3 0x8338 +#define DC_FP_H_TIMING 0x833C +#define DC_V_TIMING_1 0x8340 /* vertical timing... */ +#define DC_V_TIMING_2 0x8344 +#define DC_V_TIMING_3 0x8348 +#define DC_FP_V_TIMING 0x834C +#define DC_TIMING_CFG 0x8308 +#define DC_OUTPUT_CFG 0x830C + +/* + * what colour depth should be used as default (in bpp) + * Note: Currently no other value than 16 is supported + */ +#define COLOUR_DEPTH 16 + +/* + * Support for a few basic video modes + * Note: all modes only for CRT. The flatpanel feature is + * not supported here (due to the lack of hardware to test) + */ +struct video_mode { + int pixel_clock; /*<< pixel clock in Hz */ + unsigned long pll_value; /*<< pll register value for this clock */ + + int visible_pixel; + int hsync_start; + int hsync_end; + int line_length; + + int visible_lines; + int vsync_start; + int vsync_end; + int picture_length; + + int sync_pol; /*<< 0: low, 1: high, bit 0 hsync, bit 1 vsync */ +}; + +/* + * values for .sync_pol + */ +#define HSYNC_HIGH_POL 0 +#define HSYNC_LOW_POL 1 +#define VSYNC_HIGH_POL 0 +#define VSYNC_LOW_POL 2 + +/* ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync */ +static const struct video_mode mode_640x480 = { + /* + * 640x480 @ 72Hz hsync: 37.9kHz + * VESA standard mode for classic 4:3 monitors + */ + .pixel_clock = 31500000, + .pll_value = 0x33915801, + + .visible_pixel = 640, + .hsync_start = 664, + .hsync_end = 704, /* 1.27 us sync length */ + .line_length = 832, /* 26.39us */ + + .visible_lines = 480, + .vsync_start = 489, + .vsync_end = 491, + .picture_length = 520, /* 13.89ms */ + + .sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL +}; + +/* ModeLine "800x600" 50.0 800 856 976 1040 600 637 643 666 +hsync +vsync */ +static const struct video_mode mode_800x600 = { + /* + * 800x600 @ 72Hz hsync: 48.1kHz + * VESA standard mode for classic 4:3 monitors + */ + .pixel_clock = 50000000, + .pll_value = 0x23088801, + + .visible_pixel = 800, + .hsync_start = 856, + .hsync_end = 976, + .line_length = 1040, /* 20.8us */ + + .visible_lines = 600, + .vsync_start = 637, + .vsync_end = 643, + .picture_length = 666, /* 13.89ms */ + + .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL +}; + +/* ModeLine "1024x768" 75.0 1024 1048 1184 1328 768 771 777 806 -hsync -vsync */ +static const struct video_mode mode_1024x768 = { + /* + * 1024x768 @ 70Hz (VESA) hsync: 56.5kHz + * Standard mode for classic 4:3 monitors + */ + .pixel_clock = 75000000, + .pll_value = 0x37E22801, + + .visible_pixel = 1024, + .hsync_start = 1048, + .hsync_end = 1184, + .line_length = 1328, /* 17.7us */ + + .visible_lines = 768, + .vsync_start = 771, + .vsync_end = 777, + .picture_length = 806, /* 14.3us */ + + .sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL +}; + +/* ModeLine "1280x960" 108.0 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync */ +static const struct video_mode mode_1280x960 = { + /* + * 1280x960 @ 60Hz (VESA) hsync: 60.0kHz + * Mode for classic 4:3 monitors + */ + .pixel_clock = 108000000, + .pll_value = 0x2710C805, + + .visible_pixel = 1280, + .hsync_start = 1376, + .hsync_end = 1488, + .line_length = 1800, /* 16.67us */ + + .visible_lines = 960, + .vsync_start = 961, + .vsync_end = 964, + .picture_length = 1000, /* 16.67ms */ + + .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL +}; + +/* ModeLine "1280x1024" 108.0 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync */ +static const struct video_mode mode_1280x1024 = { + /* + * 1280x1024 @ 60Hz (VESA) hsync: 64.0kHz + * Mode for modern 5:4 flat screens + */ + .pixel_clock = 108000000, + .pll_value = 0x2710C805, + + .visible_pixel = 1280, + .hsync_start = 1328, + .hsync_end = 1440, + .line_length = 1688, /* 15.6us */ + + .visible_lines = 1024, + .vsync_start = 1025, + .vsync_end = 1028, + .picture_length = 1066, + + .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL +}; + +/* + * a few supported common modes + */ +static const struct video_mode *modes[] = { + &mode_640x480, /* CONFIG_GX1_VIDEOMODE = 0 */ + &mode_800x600, /* CONFIG_GX1_VIDEOMODE = 1 */ + &mode_1024x768, /* CONFIG_GX1_VIDEOMODE = 2 */ + &mode_1280x960, /* CONFIG_GX1_VIDEOMODE = 3 */ + &mode_1280x1024 /* CONFIG_GX1_VIDEOMODE = 4 */ +}; + +/* make a sanity check at buildtime */ +#if CONFIG_GX1_VIDEOMODE > 4 +# error Requested video mode is unknown! +#endif + +/* + * Setup the pixel PLL in the companion chip + * base: register's base address + * pll_val: pll register value to be set + */ +static void cs5530_set_clock_frequency(void *io_base,unsigned long pll_val) +{ + unsigned long reg; + + /* disable the PLL first, reset and power it down */ + reg = readl(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20; + reg |= 0x80000100; + writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + + /* write the new PLL setting */ + reg |= (pll_val & ~0x80000920); + writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + + mdelay(1); /* wait for control voltage to be 0V */ + + /* enable the PLL */ + reg |= 0x00000800; + writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + + /* clear reset */ + reg &= ~0x80000000; + writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + + /* clear bypass */ + reg &= ~0x00000100; + writel(reg, io_base+CS5530_DOT_CLK_CONFIG); +} + +/* + * Setup memory layout + * gx_base: GX register area + * mode: Data about the video mode to setup + * + * This routine assumes unlocked DC registers. Using compressed buffer + * is not supported! (makes more sense later, but not while booting) + */ +static void dc_setup_layout(void *gx_base,const struct video_mode *mode) +{ + unsigned long base = 0x00000000; + + writel(base, gx_base + DC_FB_ST_OFFSET); + + base += (COLOUR_DEPTH>>3) * mode->visible_pixel * mode->visible_lines; + + writel(base, gx_base + DC_CB_ST_OFFSET); + writel(base, gx_base + DC_CURS_ST_OFFSET); + writel(base, gx_base + DC_VID_ST_OFFSET); + writel(((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2, gx_base + DC_LINE_DELTA); + writel(((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3, gx_base + DC_BUF_SIZE); +} + +/* + * Setup the HSYNC/VSYNC, active video timing + * gx_base: GX register area + * mode: Data about the video mode to setup + * + * This routine assumes unlocked DC registers + * + * |<------------------------- htotal ----------------------------->| + * |<------------ hactive -------------->| | + * | hblankstart-->| | + * | hblankend-->| + * | hsyncstart-->| | + * | hsyncend-->| | + * |#####################################___________________________| RGB data + * |______________________________________________---------_________| HSYNC + * + * |<------------------------- vtotal ----------------------------->| + * |<------------ vactive -------------->| | + * | vblankstart-->| | + * | vblankend-->| + * | vsyncstart-->| | + * | vsyncend-->| | + * |#####################################___________________________| line data + * |______________________________________________---------_________| YSYNC + */ +static void dc_setup_timing(void *gx_base,const struct video_mode *mode) +{ + unsigned long hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; + unsigned long vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; + + hactive = mode->visible_pixel & 0x7FF; + hblankstart = hactive; + hsyncstart = mode->hsync_start & 0x7FF; + hsyncend = mode->hsync_end & 0x7FF; + hblankend = mode->line_length & 0x7FF; + htotal = hblankend; + + vactive = mode->visible_lines & 0x7FF; + vblankstart = vactive; + vsyncstart = mode->vsync_start & 0x7FF; + vsyncend = mode->vsync_end & 0x7FF; + vblankend = mode->picture_length & 0x7FF; + vtotal = vblankend; + + /* row description */ + writel((hactive - 1) | ((htotal - 1) << 16), gx_base + DC_H_TIMING_1); + /* horizontal blank description */ + writel((hblankstart - 1) | ((hblankend - 1) << 16), gx_base + DC_H_TIMING_2); + /* horizontal sync description */ + writel((hsyncstart - 1) | ((hsyncend - 1) << 16), gx_base + DC_H_TIMING_3); + writel((hsyncstart - 1) | ((hsyncend - 1) << 16), gx_base + DC_FP_H_TIMING); + + /* line description */ + writel((vactive - 1) | ((vtotal - 1) << 16), gx_base + DC_V_TIMING_1); + /* vertical blank description */ + writel((vblankstart - 1) | ((vblankend - 1) << 16), gx_base + DC_V_TIMING_2); + /* vertical sync description */ + writel((vsyncstart - 1) | ((vsyncend - 1) << 16), gx_base + DC_V_TIMING_3); + writel((vsyncstart - 2) | ((vsyncend - 2) << 16), gx_base + DC_FP_V_TIMING); +} + +/* + * Setup required internals to bring the mode up and running + * gx_base: GX register area + * mode: Data about the video mode to setup + */ +static void cs5530_activate_mode(void *gx_base, const struct video_mode *mode) +{ + writel(0x00000080, gx_base + DC_GENERAL_CFG); + mdelay(1); + dc_setup_layout(gx_base,mode); + dc_setup_timing(gx_base,mode); + + writel(0x2000C581, gx_base + DC_GENERAL_CFG); + writel(0x0000002F, gx_base + DC_TIMING_CFG); + writel(0x00003004, gx_base + DC_OUTPUT_CFG); +} + +/* + * Activate the current mode to be "visible" outside + * gx_base: GX register area + * mode: Data about the video mode to setup + */ +static void cs5530_activate_video(void *io_base, const struct video_mode *mode) +{ + u32 val; + + val = mode->sync_pol; + val <<= 8; + + writel(val | 0x0020002F, io_base + CS5530_DISPLAY_CONFIG); +} + +/* + * This bitmap file must provide: + * int width: pixel count in one line + * int height: line count + * int colours: ount of used colour + * unsigned long colour_map[]: RGB 565 colours to be used + * unsigned char bitmap[]: index per pixel into colour_map[], width*height pixels + */ +#include "bitmap.c" + +/* + * show a boot splash screen in the right lower corner of the screen + * swidth: screen width in pixel + * sheight: screen height in lines + * pitch: line pitch in bytes + * base: screen base address + * + * This routine assumes we are using a 16 bit colour depth! + */ +static void show_boot_splash_16(u32 swidth,u32 sheight,u32 pitch,void *base) +{ + int word_count,i; + unsigned short *adr; + u32 xstart,ystart,x,y; + /* + * fill the screen with the colour of the + * left top pixel in the graphic + */ + word_count = pitch*sheight; + printk_debug("Clear Screen at %p, %d words\n",base,word_count); + adr = (unsigned short *) base; + for (i=0; i < word_count; i++, adr++) + *adr = colour_map[bitmap[0]]; + printk_debug("Ready\n"); + + /* + * paint the splash + */ + xstart=swidth-width; + ystart=sheight-height; + printk_debug("Start at %u,%u\n",xstart,ystart); + for (y=0;y<height;y++) { + adr=(unsigned short*)(base + pitch*(y+ystart)+2*xstart); + for (x=0;x<width;x++) { + *adr=(unsigned short)colour_map[(int)bitmap[x+y*width]]; + adr++; + } + } +} + +/* + * management part + */ +static void cs5530_vga_init(device_t dev) +{ + const struct video_mode *mode; + void *io_base, *gx_base; + + io_base = (void*)pci_read_config32(dev,0x10); + gx_base = (void*)GX_BASE; + mode = modes[CONFIG_GX1_VIDEOMODE]; + + printk_debug("Setting up video mode %dx%d with %d Hz clock\n", + mode->visible_pixel, mode->visible_lines, mode->pixel_clock); + + cs5530_set_clock_frequency(io_base,mode->pll_value); + + writel(DC_UNLOCK_MAGIC, gx_base + DC_UNLOCK); + + show_boot_splash_16(mode->visible_pixel, mode->visible_lines, + mode->visible_pixel*(COLOUR_DEPTH>>3),(void*)(GX_BASE+0x800000)); + + cs5530_activate_mode(gx_base,mode); + + cs5530_activate_video(io_base, mode); + writel(0x00000000, gx_base + DC_UNLOCK); +} + +static struct device_operations vga_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = cs5530_vga_init, + .enable = NULL /* not required */ +}; + +static struct pci_driver vga_pci_driver __pci_driver = { + .ops = &vga_ops, + .vendor = PCI_VENDOR_ID_CYRIX, + .device = PCI_DEVICE_ID_CYRIX_5530_VIDEO +}; + +#endif /* #if CONFIG_GX1_VIDEO == 1 */ |