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Diffstat (limited to 'src/southbridge/amd/rs690')
-rw-r--r--src/southbridge/amd/rs690/rs690.c3
-rw-r--r--src/southbridge/amd/rs690/rs690_pcie.c4
2 files changed, 5 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c
index caf838aacf..0d6db72393 100644
--- a/src/southbridge/amd/rs690/rs690.c
+++ b/src/southbridge/amd/rs690/rs690.c
@@ -104,8 +104,7 @@ void static rs690_config_misc_clk(device_t nb_dev)
set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
}
-
-u32 get_vid_did(device_t dev)
+static u32 get_vid_did(device_t dev)
{
return pci_read_config32(dev, 0);
}
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c
index ad2e871db4..f02e0d73b4 100644
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/rs690_pcie.c
@@ -105,6 +105,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
}
}
+#ifdef UNUSED_CODE
static void pcie_init(struct device *dev)
{
/* Enable pci error detecting */
@@ -118,6 +119,7 @@ static void pcie_init(struct device *dev)
dword |= (1 << 30); /* Clear possible errors */
pci_write_config32(dev, 0x04, dword);
}
+#endif
/**********************************************************************
**********************************************************************/
@@ -355,6 +357,7 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
ValidatePortEn(nb_dev);
}
+#ifdef UNUSED_CODE
/*****************************************
* Compliant with CIM_33's PCIEMiscClkProg
*****************************************/
@@ -395,3 +398,4 @@ void pcie_config_misc_clk(device_t nb_dev)
reg &= ~(1 << 0);
pci_write_config32(nb_dev, 0x4c, reg);
}
+#endif