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Diffstat (limited to 'src/southbridge/amd/rs780/rs780_gfx.c')
-rw-r--r--src/southbridge/amd/rs780/rs780_gfx.c54
1 files changed, 27 insertions, 27 deletions
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c
index aa46451410..808bcb175f 100644
--- a/src/southbridge/amd/rs780/rs780_gfx.c
+++ b/src/southbridge/amd/rs780/rs780_gfx.c
@@ -55,7 +55,7 @@ static u32 clkind_read(device_t dev, u32 index)
static void clkind_write(device_t dev, u32 index, u32 data)
{
u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
- /* printk_info("gfx bar 2 %02x\n", gfx_bar2); */
+ /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */
*(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
*(u32*)(gfx_bar2+CLK_CNTL_DATA) = data;
@@ -67,7 +67,7 @@ static void clkind_write(device_t dev, u32 index, u32 data)
*/
static void rs780_gfx_read_resources(device_t dev)
{
- printk_info("rs780_gfx_read_resources.\n");
+ printk(BIOS_INFO, "rs780_gfx_read_resources.\n");
/* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
@@ -189,7 +189,7 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
{
tempdev = dev_find_slot(Bus, Dev << 3);
Value = pci_read_config32(tempdev, 0);
- printk_debug("Dev ID %x \n", Value);
+ printk(BIOS_DEBUG, "Dev ID %x \n", Value);
if((Value & 0xffff) == 0x1102)
{//Creative
//Found Creative SB
@@ -220,7 +220,7 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
}
}
}
- printk_debug(" MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
+ printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
if (MMIOStart < MMIOLimit)
{
Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
@@ -310,7 +310,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
- printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
+ printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
deviceid, vendorid);
command = pci_read_config16(dev, 0x04);
@@ -420,7 +420,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */
vgainfo.ulReserved1[0] = 0; vgainfo.ulReserved1[1] = 0;
value = pci_read_config32(k8_f2, 0x94);
- printk_debug("MEMCLK = %x\n", value&0x7);
+ printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7);
vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */
vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */
vgainfo.ulMinSidePortClock = 0; /* disable SP. */
@@ -447,14 +447,14 @@ static void internal_gfx_pci_dev_init(struct device *dev)
vgainfo.usBootUpNBVoltage = 0x1a;
value = pci_read_config32(nb_dev, 0xd0);
- printk_debug("NB HT speed = %x.\n", value);
+ printk(BIOS_DEBUG, "NB HT speed = %x.\n", value);
value = pci_read_config32(k8_f0, 0x88);
- printk_debug("CPU HT speed = %x.\n", value);
+ printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value);
vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */
/* HT width. */
value = pci_read_config32(nb_dev, 0xc8);
- printk_debug("HT width = %x.\n", value);
+ printk(BIOS_DEBUG, "HT width = %x.\n", value);
vgainfo.usMinHTLinkWidth = 16;
vgainfo.usMaxHTLinkWidth = 16;
vgainfo.usUMASyncStartDelay = 322;
@@ -585,10 +585,10 @@ static void rs780_internal_gfx_enable(device_t dev)
u32 FB_Start, FB_End;
#endif
- printk_info("rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
+ printk(BIOS_INFO, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
sysmem = rdmsr(0xc001001a);
- printk_info("sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
+ printk(BIOS_INFO, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
/* The system top memory in 780. */
pci_write_config32(nb_dev, 0x90, sysmem.lo);
@@ -826,12 +826,12 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
struct southbridge_amd_rs780_config *cfg =
(struct southbridge_amd_rs780_config *)nb_dev->chip_info;
- printk_info("rs780_gfx_init single_port_configuration.\n");
+ printk(BIOS_INFO, "rs780_gfx_init single_port_configuration.\n");
/* step 12 training, releases hold training for GFX port 0 (device 2) */
PcieReleasePortTraining(nb_dev, dev, 2);
result = PcieTrainPort(nb_dev, dev, 2);
- printk_info("rs780_gfx_init single_port_configuration step12.\n");
+ printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step12.\n");
/* step 13 Power Down Control */
/* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
@@ -851,7 +851,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
reg32 = nbpcie_p_read_index(dev, 0x29);
width = reg32 & 0xFF;
- printk_debug("GFX Inactive Lanes = 0x%x.\n", width);
+ printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width);
switch (width) {
case 1:
case 2:
@@ -868,11 +868,11 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
break;
}
}
- printk_info("rs780_gfx_init single_port_configuration step13.\n");
+ printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step13.\n");
/* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
- printk_info("rs780_gfx_init single_port_configuration step14.\n");
+ printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step14.\n");
}
static void dual_port_configuration(device_t nb_dev, device_t dev)
@@ -905,7 +905,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
} else { /* step 16.b Link Training was successful */
reg32 = nbpcie_p_read_index(dev, 0xa2);
width = (reg32 >> 4) & 0x7;
- printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width);
+ printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
switch (width) {
case 1:
case 2:
@@ -983,7 +983,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
struct southbridge_amd_rs780_config *cfg =
(struct southbridge_amd_rs780_config *)nb_dev->chip_info;
- printk_info("rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
+ printk(BIOS_INFO, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
nb_dev, dev, port);
/* GFX Core Initialization */
@@ -995,13 +995,13 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
if (cfg->gfx_dual_slot)
set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
}
- printk_info("rs780_gfx_init step1.\n");
+ printk(BIOS_INFO, "rs780_gfx_init step1.\n");
/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
/* AMD calls the configuration CrossFire */
if (cfg->gfx_dual_slot)
set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
- printk_info("rs780_gfx_init step2.\n");
+ printk(BIOS_INFO, "rs780_gfx_init step2.\n");
/* step 2, TMDS, (only need if CMOS option is enabled) */
if (cfg->gfx_tmds) {
@@ -1020,7 +1020,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1 << 6 | 1 << 8 | 1 << 10);
reg32 = nbmisc_read_index(nb_dev, 0x28);
- printk_info("misc 28 = %x\n", reg32);
+ printk(BIOS_INFO, "misc 28 = %x\n", reg32);
/* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
@@ -1038,7 +1038,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
0);
reg32 = nbmisc_read_index(nb_dev, 0x28);
- printk_info("misc 28 = %x\n", reg32);
+ printk(BIOS_INFO, "misc 28 = %x\n", reg32);
/* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
@@ -1079,7 +1079,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* release hold training for device 2. GFX initialization is done. */
set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
- printk_info("rs780_gfx_init step7.\n");
+ printk(BIOS_INFO, "rs780_gfx_init step7.\n");
return;
}
@@ -1087,11 +1087,11 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* 5.9.12.1 sets RCB timeout to be 25ms */
/* 5.9.12.2. RCB Cpl timeout on link down. */
set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
- printk_info("rs780_gfx_init step5.9.12.1.\n");
+ printk(BIOS_INFO, "rs780_gfx_init step5.9.12.1.\n");
/* step 5.9.12.3 disables slave ordering logic */
set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
- printk_info("rs780_gfx_init step5.9.12.3.\n");
+ printk(BIOS_INFO, "rs780_gfx_init step5.9.12.3.\n");
/* step 5.9.12.4 sets DMA payload size to 64 bytes */
set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
@@ -1113,7 +1113,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
- printk_info("rs780_gfx_init step5.9.12.9.\n");
+ printk(BIOS_INFO, "rs780_gfx_init step5.9.12.9.\n");
/* 5.9.12.10 Sets the timer in Config state from 20us to */
/* 5.9.12.11 De-asserts RX_EN in L0s. */
@@ -1188,7 +1188,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
dual_port_configuration(nb_dev, dev);
break;
default:
- printk_info("Incorrect configuration of external gfx slot.\n");
+ printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n");
break;
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 14:03:50 +0000