diff options
Diffstat (limited to 'src/southbridge/amd/sb600')
| -rw-r--r-- | src/southbridge/amd/sb600/sb600_hda.c | 18 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/sb600_sata.c | 24 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/sb600_usb.c | 8 |
3 files changed, 25 insertions, 25 deletions
diff --git a/src/southbridge/amd/sb600/sb600_hda.c b/src/southbridge/amd/sb600/sb600_hda.c index 4c17c04bbb..3d24825c63 100644 --- a/src/southbridge/amd/sb600/sb600_hda.c +++ b/src/southbridge/amd/sb600/sb600_hda.c @@ -37,10 +37,10 @@ static int set_bits(u8 * port, u32 mask, u32 val) /* Write (val & ~mask) to port */ val &= mask; - dword = readl(port); + dword = read32(port); dword &= ~mask; dword |= val; - writel(dword, port); + write32(port, dword); /* Wait for readback of register to * match what was just written to it @@ -49,7 +49,7 @@ static int set_bits(u8 * port, u32 mask, u32 val) do { /* Wait 1ms based on BKDG wait time */ mdelay(1); - dword = readl(port); + dword = read32(port); dword &= mask; } while ((dword != val) && --count); @@ -75,7 +75,7 @@ static u32 codec_detect(u8 * base) mdelay(1); /* Read in Codec location (BAR + 0xe)[3..0]*/ - dword = readl(base + 0xe); + dword = read32(base + 0xe); dword &= 0x0F; if (!dword) goto no_codec; @@ -180,7 +180,7 @@ static int wait_for_ready(u8 *base) int timeout = 50; while(timeout--) { - u32 dword=readl(base + HDA_ICII_REG); + u32 dword=read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; udelay(1); @@ -202,7 +202,7 @@ static int wait_for_valid(u8 *base) int timeout = 50; while(timeout--) { - u32 dword = readl(base + HDA_ICII_REG); + u32 dword = read32(base + HDA_ICII_REG); if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; @@ -224,12 +224,12 @@ static void codec_init(u8 * base, int addr) return; dword = (addr << 28) | 0x000f0000; - writel(dword, base + 0x60); + write32(base + 0x60, dword); if (wait_for_valid(base) == -1) return; - dword = readl(base + 0x64); + dword = read32(base + 0x64); /* 2 */ printk_debug("codec viddid: %08x\n", dword); @@ -246,7 +246,7 @@ static void codec_init(u8 * base, int addr) if (wait_for_ready(base) == -1) return; - writel(verb[i], base + 0x60); + write32(base + 0x60, verb[i]); if (wait_for_valid(base) == -1) return; diff --git a/src/southbridge/amd/sb600/sb600_sata.c b/src/southbridge/amd/sb600/sb600_sata.c index 3d7f2c416c..b0074b70e3 100644 --- a/src/southbridge/amd/sb600/sb600_sata.c +++ b/src/southbridge/amd/sb600/sb600_sata.c @@ -172,7 +172,7 @@ static void sata_init(struct device *dev) /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ for (i = 0; i < 4; i++) { - byte = readb(sata_bar5 + 0x128 + 0x80 * i); + byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk_spew("SATA port %i status = %x\n", i, byte); byte &= 0xF; @@ -182,24 +182,24 @@ static void sata_init(struct device *dev) printk_spew("SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ - byte = readb(sata_bar5 + 0x12C + 0x80 * i); + byte = read8(sata_bar5 + 0x12C + 0x80 * i); /* Set Reset Bit and 1.5g bit */ byte |= 0x11; - writeb(byte, (sata_bar5 + 0x12C + 0x80 * i)); + write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Clear Reset Bit */ byte &= ~0x01; - writeb(byte, (sata_bar5 + 0x12C + 0x80 * i)); + write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Reread status */ - byte = readb(sata_bar5 + 0x128 + 0x80 * i); + byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk_spew("SATA port %i status = %x\n", i, byte); byte &= 0xF; } @@ -223,15 +223,15 @@ static void sata_init(struct device *dev) /* Below is CIM InitSataLateFar */ /* Enable interrupts from the HBA */ - byte = readb(sata_bar5 + 0x4); + byte = read8(sata_bar5 + 0x4); byte |= 1 << 1; - writeb(byte, (sata_bar5 + 0x4)); + write8((sata_bar5 + 0x4), byte); /* Clear error status */ - writel(0xFFFFFFFF, (sata_bar5 + 0x130)); - writel(0xFFFFFFFF, (sata_bar5 + 0x1b0)); - writel(0xFFFFFFFF, (sata_bar5 + 0x230)); - writel(0xFFFFFFFF, (sata_bar5 + 0x2b0)); + write32((sata_bar5 + 0x130), 0xFFFFFFFF); + write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); + write32((sata_bar5 + 0x230), 0xFFFFFFFF); + write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */ @@ -241,7 +241,7 @@ static void sata_init(struct device *dev) /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ /* printk_debug("AcpiGpe0Blk addr = %x\n", word); */ - /* writel(0x80000000 , word); */ + /* write32(word, 0x80000000); */ } static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/sb600/sb600_usb.c b/src/southbridge/amd/sb600/sb600_usb.c index 2002114f81..4be2d73272 100644 --- a/src/southbridge/amd/sb600/sb600_usb.c +++ b/src/southbridge/amd/sb600/sb600_usb.c @@ -98,16 +98,16 @@ static void usb_init2(struct device *dev) /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; - writel(dword, usb2_bar0 + 0xC0); + write32(usb2_bar0 + 0xC0, dword); /* RPR5.5 Sets In/OUT FIFO threshold for best performance */ dword = 0x00200040; - writel(dword, usb2_bar0 + 0xA4); + write32(usb2_bar0 + 0xA4, dword); /* RPR5.9 Disable the EHCI Dynamic Power Saving feature */ - word = readl(usb2_bar0 + 0xBC); + word = read16(usb2_bar0 + 0xBC); word &= ~(1 << 12); - writew(word, usb2_bar0 + 0xBC); + write16(usb2_bar0 + 0xBC, word); /* RPR5.10 Disable EHCI MSI support */ byte = pci_read_config8(dev, 0x50); |