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Diffstat (limited to 'src/southbridge/amd/sr5650/cmn.h')
-rw-r--r--src/southbridge/amd/sr5650/cmn.h104
1 files changed, 85 insertions, 19 deletions
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
index 859e15dd62..126b786246 100644
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -34,30 +34,54 @@
#define AB_INDX 0xCD8
#define AB_DATA (AB_INDX+4)
-static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
+#else
+static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
+#endif
{
pci_write_config32(dev, index_reg, index);
return pci_read_config32(dev, index_reg + 0x4);
}
-static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+#ifdef __SIMPLE_DEVICE__
+static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index,
+ u32 data)
+#else
+static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index,
+ u32 data)
+#endif
{
pci_write_config32(dev, index_reg, index);
pci_write_config32(dev, index_reg + 0x4, data);
}
-static inline u32 nbmisc_read_index(device_t nb_dev, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
+#else
+static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)
+#endif
{
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
}
-static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+#ifdef __SIMPLE_DEVICE__
+static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+#else
+static inline void nbmisc_write_index(struct device *nb_dev, u32 index,
+ u32 data)
+#endif
{
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
}
-static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#else
+static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
@@ -68,28 +92,49 @@ static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask
}
}
-static inline u32 htiu_read_index(device_t nb_dev, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
+#else
+static inline u32 htiu_read_index(struct device *nb_dev, u32 index)
+#endif
{
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
}
-static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+#ifdef __SIMPLE_DEVICE__
+static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+#else
+static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
+#endif
{
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
}
-static inline u32 nbmc_read_index(device_t nb_dev, u32 index)
+#ifdef __SIMPLE_DEVICE__
+static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
+#else
+static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)
+#endif
{
return nb_read_index((nb_dev), NBMC_INDEX, (index));
}
-static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+#ifdef __SIMPLE_DEVICE__
+static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
+#else
+static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
+#endif
{
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
}
-static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#else
+static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = htiu_read_index(nb_dev, reg_pos);
@@ -100,8 +145,13 @@ static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#else
+static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = pci_read_config32(nb_dev, reg_pos);
@@ -112,8 +162,13 @@ static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
- u8 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos,
+ u8 mask, u8 val)
+#else
+static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos,
+ u8 mask, u8 val)
+#endif
{
u8 reg_old, reg;
reg = reg_old = pci_read_config8(nb_dev, reg_pos);
@@ -124,8 +179,13 @@ static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask
}
}
-static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
- u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#else
+static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
@@ -136,7 +196,13 @@ static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
+#ifdef __SIMPLE_DEVICE__
+static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask,
+ u32 val)
+#else
+static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos,
+ u32 mask, u32 val)
+#endif
{
u32 reg_old, reg;
reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);