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Diffstat (limited to 'src/southbridge/amd/sr5650/pcie.c')
-rw-r--r--src/southbridge/amd/sr5650/pcie.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 763dd014af..f87fadbb08 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -893,7 +893,10 @@ void pcie_config_misc_clk(struct device *nb_dev)
reg |= 1 << 0;
pci_write_config32(nb_dev, 0x4c, reg);
-#if 0 /* TODO: Check the mics clock later. */
+#if 0
+ /* TODO: Check the mics clock later. */
+ pci_devfn_t d0f1 = PCI_DEV(0, 0, 1);
+
if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
/* TXCLK Clock Gating */
set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
@@ -901,9 +904,9 @@ void pcie_config_misc_clk(struct device *nb_dev)
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
/* LCLK Clock Gating */
- reg = pci_cf8_conf1.read32(0, 1, 0x94);
+ reg = pci_io_read_config32(d0f1, 0x94);
reg &= ~(1 << 16);
- pci_cf8_conf1.write32(0, 1, 0x94, reg);
+ pci_io_write_config32(d0f1, 0x94, reg);
}
if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
@@ -913,9 +916,9 @@ void pcie_config_misc_clk(struct device *nb_dev)
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6);
/* LCLK Clock Gating */
- reg = pci_cf8_conf1.read32(0, 1, 0x94);
+ reg = pci_io_read_config32(d0f1, 0x94);
reg &= ~(1 << 24);
- pci_cf8_conf1.write32(0, 1, 0x94, reg);
+ pci_io_write_config32(d0f1, 0x94, reg);
}
#endif