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-rw-r--r--src/southbridge/amd/agesa/hudson/chip.h2
-rw-r--r--src/southbridge/amd/amd8111/chip.h3
-rw-r--r--src/southbridge/amd/cimx/sb700/chip.h2
-rw-r--r--src/southbridge/amd/cimx/sb800/chip.h2
-rw-r--r--src/southbridge/amd/cimx/sb900/chip.h2
-rw-r--r--src/southbridge/amd/cs5530/chip.h2
-rw-r--r--src/southbridge/amd/cs5535/chip.h2
-rw-r--r--src/southbridge/amd/cs5536/chip.h2
-rw-r--r--src/southbridge/amd/rs690/chip.h2
-rw-r--r--src/southbridge/amd/rs780/chip.h2
-rw-r--r--src/southbridge/amd/sb600/chip.h2
-rw-r--r--src/southbridge/amd/sb700/chip.h2
-rw-r--r--src/southbridge/amd/sb800/chip.h2
-rw-r--r--src/southbridge/amd/sr5650/chip.h2
14 files changed, 0 insertions, 29 deletions
diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h
index 7732f6d2fe..1970608978 100644
--- a/src/southbridge/amd/agesa/hudson/chip.h
+++ b/src/southbridge/amd/agesa/hudson/chip.h
@@ -30,7 +30,5 @@ struct southbridge_amd_agesa_hudson_config
u8 gpp_configuration;
#endif
};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_agesa_hudson_ops;
#endif /* HUDSON_CHIP_H */
diff --git a/src/southbridge/amd/amd8111/chip.h b/src/southbridge/amd/amd8111/chip.h
index 601038c441..622bf10fb7 100644
--- a/src/southbridge/amd/amd8111/chip.h
+++ b/src/southbridge/amd/amd8111/chip.h
@@ -8,7 +8,4 @@ struct southbridge_amd_amd8111_config
unsigned int phy_lowreset : 1;
};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_amd8111_ops;
-
#endif /* AMD8111_CHIP_H */
diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h
index ef294f450c..05edc5c288 100644
--- a/src/southbridge/amd/cimx/sb700/chip.h
+++ b/src/southbridge/amd/cimx/sb700/chip.h
@@ -20,8 +20,6 @@
#ifndef _CIMX_SB700_CHIP_H_
#define _CIMX_SB700_CHIP_H_
-extern struct chip_operations southbridge_amd_cimx_sb700_ops;
-
/*
* configuration set in mainboard/devicetree.cb
* boot_switch_sata_ide:
diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h
index 3581f2e3b0..7fc7b88c76 100644
--- a/src/southbridge/amd/cimx/sb800/chip.h
+++ b/src/southbridge/amd/cimx/sb800/chip.h
@@ -20,8 +20,6 @@
#ifndef _CIMX_SB800_CHIP_H_
#define _CIMX_SB800_CHIP_H_
-extern struct chip_operations southbridge_amd_cimx_sb800_ops;
-
/*
* configuration set in mainboard/devicetree.cb
* boot_switch_sata_ide:
diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h
index 96afc42736..9004969b85 100644
--- a/src/southbridge/amd/cimx/sb900/chip.h
+++ b/src/southbridge/amd/cimx/sb900/chip.h
@@ -20,8 +20,6 @@
#ifndef _CIMX_SB900_CHIP_H_
#define _CIMX_SB900_CHIP_H_
-extern struct chip_operations southbridge_amd_cimx_sb900_ops;
-
/*
* configuration set in mainboard/devicetree.cb
* boot_switch_sata_ide:
diff --git a/src/southbridge/amd/cs5530/chip.h b/src/southbridge/amd/cs5530/chip.h
index 92d64e49f9..271facb147 100644
--- a/src/southbridge/amd/cs5530/chip.h
+++ b/src/southbridge/amd/cs5530/chip.h
@@ -21,8 +21,6 @@
#ifndef SOUTHBRIDGE_AMD_CS5530_CHIP_H
#define SOUTHBRIDGE_AMD_CS5530_CHIP_H
-extern struct chip_operations southbridge_amd_cs5530_ops;
-
struct southbridge_amd_cs5530_config {
int ide0_enable:1;
int ide1_enable:1;
diff --git a/src/southbridge/amd/cs5535/chip.h b/src/southbridge/amd/cs5535/chip.h
index 3894a06906..d4dde3d6ee 100644
--- a/src/southbridge/amd/cs5535/chip.h
+++ b/src/southbridge/amd/cs5535/chip.h
@@ -1,8 +1,6 @@
#ifndef _SOUTHBRIDGE_AMD_CS5535
#define _SOUTHBRIDGE_AMD_CS5535
-extern struct chip_operations southbridge_amd_cs5535_ops;
-
struct southbridge_amd_cs5535_config {
int setupflash;
};
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h
index ad9e736dec..69deadc70b 100644
--- a/src/southbridge/amd/cs5536/chip.h
+++ b/src/southbridge/amd/cs5536/chip.h
@@ -23,8 +23,6 @@
#define MAX_UNWANTED_VPCI 8 /* increase if needed */
-extern struct chip_operations southbridge_amd_cs5536_ops;
-
struct southbridge_amd_cs5536_config {
unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */
unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */
diff --git a/src/southbridge/amd/rs690/chip.h b/src/southbridge/amd/rs690/chip.h
index 5e08cc59f8..8ff4be5401 100644
--- a/src/southbridge/amd/rs690/chip.h
+++ b/src/southbridge/amd/rs690/chip.h
@@ -33,7 +33,5 @@ struct southbridge_amd_rs690_config
u8 gfx_reconfiguration; /* Dynamic Lind Width Control */
u8 gfx_link_width; /* Desired width of lane 2 */
};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_rs690_ops;
#endif /* RS690_CHIP_H */
diff --git a/src/southbridge/amd/rs780/chip.h b/src/southbridge/amd/rs780/chip.h
index 4a10ae0f8a..7afcbf2236 100644
--- a/src/southbridge/amd/rs780/chip.h
+++ b/src/southbridge/amd/rs780/chip.h
@@ -36,7 +36,5 @@ struct southbridge_amd_rs780_config
u8 gfx_pcie_config; /* GFX PCIE Modes */
u8 gfx_ddi_config; /* GFX DDI Modes */
};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_rs780_ops;
#endif /* RS780_CHIP_H */
diff --git a/src/southbridge/amd/sb600/chip.h b/src/southbridge/amd/sb600/chip.h
index ce40f18bf3..e288cbff89 100644
--- a/src/southbridge/amd/sb600/chip.h
+++ b/src/southbridge/amd/sb600/chip.h
@@ -24,7 +24,5 @@ struct southbridge_amd_sb600_config
{
u32 hda_viddid;
};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sb600_ops;
#endif /* SB600_CHIP_H */
diff --git a/src/southbridge/amd/sb700/chip.h b/src/southbridge/amd/sb700/chip.h
index acdb2b712c..390c579e52 100644
--- a/src/southbridge/amd/sb700/chip.h
+++ b/src/southbridge/amd/sb700/chip.h
@@ -24,7 +24,5 @@ struct southbridge_amd_sb700_config
{
u32 boot_switch_sata_ide : 1;
};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sb700_ops;
#endif /* SB700_CHIP_H */
diff --git a/src/southbridge/amd/sb800/chip.h b/src/southbridge/amd/sb800/chip.h
index 41f26d16c0..13e1aacd72 100644
--- a/src/southbridge/amd/sb800/chip.h
+++ b/src/southbridge/amd/sb800/chip.h
@@ -28,7 +28,5 @@ struct southbridge_amd_sb800_config
u32 hda_viddid;
u8 gpp_configuration;
};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sb800_ops;
#endif /* SB800_CHIP_H */
diff --git a/src/southbridge/amd/sr5650/chip.h b/src/southbridge/amd/sr5650/chip.h
index 43f8dd343c..236ac16b3e 100644
--- a/src/southbridge/amd/sr5650/chip.h
+++ b/src/southbridge/amd/sr5650/chip.h
@@ -28,7 +28,5 @@ struct southbridge_amd_sr5650_config
u8 gpp3a_configuration; /* The configuration of General Purpose Port. */
u16 port_enable; /* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */
};
-struct chip_operations;
-extern struct chip_operations southbridge_amd_sr5650_ops;
#endif /* SR5650_CHIP_H */