diff options
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/sb600/Kconfig | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/sb600.h | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/sb600_enable_usbdebug.c | 11 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/Kconfig | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sb700.h | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/sb700_enable_usbdebug.c | 13 |
8 files changed, 31 insertions, 13 deletions
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index ed4072dc2e..5af6b134e0 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -22,3 +22,11 @@ config SOUTHBRIDGE_AMD_SB600 select IOAPIC select HAVE_USBDEBUG +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB600 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB600 + diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc index b13d3de01f..854539b9b3 100644 --- a/src/southbridge/amd/sb600/Makefile.inc +++ b/src/southbridge/amd/sb600/Makefile.inc @@ -8,3 +8,4 @@ driver-y += sb600_hda.c driver-y += sb600_ac97.c driver-y += sb600_pci.c ramstage-y += sb600_reset.c +romstage-y += sb600_enable_usbdebug.c diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h index 629f389973..0ba107acc7 100644 --- a/src/southbridge/amd/sb600/sb600.h +++ b/src/southbridge/amd/sb600/sb600.h @@ -40,4 +40,5 @@ void sb600_enable(device_t dev); void sb600_lpc_port80(void); void sb600_pci_port80(void); +void sb600_enable_usbdebug(unsigned int port); #endif /* SB600_H */ diff --git a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c index 6a150aded0..b4d97b0da2 100644 --- a/src/southbridge/amd/sb600/sb600_enable_usbdebug.c +++ b/src/southbridge/amd/sb600/sb600_enable_usbdebug.c @@ -18,12 +18,11 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> - -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ +#include "sb600.h" /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -31,7 +30,7 @@ void set_debug_port(unsigned int port) /* TODO: Allow changing the physical USB port used as Debug Port. */ } -static void sb600_enable_usbdebug(unsigned int port) +void sb600_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ @@ -39,7 +38,7 @@ static void sb600_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 5ceb446a82..97768d18e5 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -27,3 +27,11 @@ config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT default n depends on SOUTHBRIDGE_AMD_SB700 +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB700 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB700 + diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 8e6868bb17..dd97df31e6 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -7,3 +7,4 @@ driver-y += sb700_sata.c driver-y += sb700_hda.c driver-y += sb700_pci.c ramstage-y += sb700_reset.c +romstage-y += sb700_enable_usbdebug.c diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index d4107a942e..088bba611d 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -59,4 +59,5 @@ void sb700_setup_sata_phys(struct device *dev); #endif +void sb700_enable_usbdebug(unsigned int port); #endif /* SB700_H */ diff --git a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c index 02d3900047..d74a9bbc9f 100644 --- a/src/southbridge/amd/sb700/sb700_enable_usbdebug.c +++ b/src/southbridge/amd/sb700/sb700_enable_usbdebug.c @@ -19,14 +19,13 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "sb700.h" -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ - -#define EHCI_EOR (EHCI_BAR + 0x20) +#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) void set_debug_port(unsigned int port) @@ -46,12 +45,12 @@ void set_debug_port(unsigned int port) * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ -static void sb700_enable_usbdebug(unsigned int port) +void sb700_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |