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-rw-r--r--src/southbridge/amd/amd8111/Kconfig24
-rw-r--r--src/southbridge/amd/amd8111/Makefile.inc15
-rw-r--r--src/southbridge/amd/amd8111/ac97.c56
-rw-r--r--src/southbridge/amd/amd8111/acpi.c254
-rw-r--r--src/southbridge/amd/amd8111/acpi/sleepstates.asl39
-rw-r--r--src/southbridge/amd/amd8111/amd8111.c86
-rw-r--r--src/southbridge/amd/amd8111/amd8111.h22
-rw-r--r--src/southbridge/amd/amd8111/amd8111_smbus.h344
-rw-r--r--src/southbridge/amd/amd8111/bootblock.c57
-rw-r--r--src/southbridge/amd/amd8111/chip.h24
-rw-r--r--src/southbridge/amd/amd8111/early_ctrl.c100
-rw-r--r--src/southbridge/amd/amd8111/early_smbus.c77
-rw-r--r--src/southbridge/amd/amd8111/ide.c80
-rw-r--r--src/southbridge/amd/amd8111/lpc.c176
-rw-r--r--src/southbridge/amd/amd8111/nic.c103
-rw-r--r--src/southbridge/amd/amd8111/pci.c79
-rw-r--r--src/southbridge/amd/amd8111/reset.c59
-rw-r--r--src/southbridge/amd/amd8111/smbus.c52
-rw-r--r--src/southbridge/amd/amd8111/usb.c46
-rw-r--r--src/southbridge/amd/amd8111/usb2.c43
20 files changed, 0 insertions, 1736 deletions
diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig
deleted file mode 100644
index a3abf89d9e..0000000000
--- a/src/southbridge/amd/amd8111/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SOUTHBRIDGE_AMD_AMD8111
- bool
- select IOAPIC
- select HAVE_POWER_STATE_AFTER_FAILURE
-
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/amd8111/bootblock.c"
- depends on SOUTHBRIDGE_AMD_AMD8111
diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc
deleted file mode 100644
index 4c9ebaed88..0000000000
--- a/src/southbridge/amd/amd8111/Makefile.inc
+++ /dev/null
@@ -1,15 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y)
-
-ramstage-y += amd8111.c
-ramstage-y += usb.c
-ramstage-y += lpc.c
-ramstage-y += ide.c
-ramstage-y += acpi.c
-ramstage-y += usb2.c
-ramstage-y += ac97.c
-ramstage-y += nic.c
-ramstage-y += pci.c
-ramstage-y += smbus.c
-ramstage-y += reset.c
-
-endif
diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c
deleted file mode 100644
index d05f0be6d9..0000000000
--- a/src/southbridge/amd/amd8111/ac97.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2003 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "amd8111.h"
-
-static struct pci_operations lops_pci = {
- .set_subsystem = pci_dev_set_subsystem,
-};
-
-static struct device_operations ac97audio_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = amd8111_enable,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver ac97audio_driver __pci_driver = {
- .ops = &ac97audio_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x746D,
-};
-
-
-static struct device_operations ac97modem_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = amd8111_enable,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver ac97modem_driver __pci_driver = {
- .ops = &ac97modem_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x746E,
-};
diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
deleted file mode 100644
index a735ff9bf9..0000000000
--- a/src/southbridge/amd/amd8111/acpi.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/smbus.h>
-#include <pc80/mc146818rtc.h>
-#include <lib.h>
-#include <arch/io.h>
-#include "amd8111.h"
-#include "amd8111_smbus.h"
-
-#define PREVIOUS_POWER_STATE 0x43
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-#define SLOW_CPU_OFF 0
-#define SLOW_CPU__ON 1
-
-static int lsmbus_recv_byte(struct device *dev)
-{
- unsigned int device;
- struct resource *res;
-
- device = dev->path.i2c.device;
- res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
- return do_smbus_recv_byte(res->base, device);
-}
-
-static int lsmbus_send_byte(struct device *dev, uint8_t val)
-{
- unsigned int device;
- struct resource *res;
-
- device = dev->path.i2c.device;
- res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
- return do_smbus_send_byte(res->base, device, val);
-}
-
-
-static int lsmbus_read_byte(struct device *dev, uint8_t address)
-{
- unsigned int device;
- struct resource *res;
-
- device = dev->path.i2c.device;
- res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
- return do_smbus_read_byte(res->base, device, address);
-}
-
-static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val)
-{
- unsigned int device;
- struct resource *res;
-
- device = dev->path.i2c.device;
- res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
- return do_smbus_write_byte(res->base, device, address, val);
-}
-
-static int lsmbus_block_read(struct device *dev, uint8_t cmd, u8 bytes,
- u8 *buffer)
-{
- unsigned int device;
- struct resource *res;
-
- device = dev->path.i2c.device;
- res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
- return do_smbus_block_read(res->base, device, cmd, bytes, buffer);
-}
-
-static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes,
- const u8 *buffer)
-{
- unsigned int device;
- struct resource *res;
-
- device = dev->path.i2c.device;
- res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
-
- return do_smbus_block_write(res->base, device, cmd, bytes, buffer);
-}
-
-
-#if CONFIG(HAVE_ACPI_TABLES)
-unsigned int pm_base;
-#endif
-
-static void acpi_init(struct device *dev)
-{
- uint8_t byte;
- uint16_t pm10_bar;
- int on;
-
-#if 0
- uint16_t word;
- printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
- byte = pci_read_config8(dev, 0x49);
- pci_write_config8(dev, 0x49, byte | (1<<2));
-
-
- byte = pci_read_config8(dev, 0x41);
- pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2));
-
- /* added from sourceforge */
- byte = pci_read_config8(dev, 0x48);
- pci_write_config8(dev, 0x48, byte | (1<<3));
-
- printk(BIOS_DEBUG, "done.\n");
-
-
- printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. ");
- word = pci_read_config16(dev, 0x46);
- pci_write_config16(dev, 0x46, word | (1<<9));
- printk(BIOS_DEBUG, "done.\n");
-#endif
-
- /* To enable the register 0xcf9 in the IO space
- * bit [D5] is set in the amd8111 configuration register.
- * The config. reg. is devBx41. Register 0xcf9 allows
- * hard reset capability to the system. For the ACPI
- * reset.reg values in fadt.c to work this register
- * must be enabled.
- */
- byte = pci_read_config8(dev, 0x41);
- pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
-
- /* power on after power fail */
- on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
- get_option(&on, "power_on_after_fail");
- byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
- byte &= ~0x40;
- if (!on) {
- byte |= 0x40;
- }
- pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
- printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
-
- /* switch serial irq logic from quiet mode to continuous
- * mode for Winbond W83627HF Rev. 17
- */
- byte = pci_read_config8(dev, 0x4a);
- pci_write_config8(dev, 0x4a, byte | (1<<6));
-
- /* Throttle the CPU speed down for testing */
- on = SLOW_CPU_OFF;
- get_option(&on, "slow_cpu");
- if (on) {
- pm10_bar = (pci_read_config16(dev, 0x58) & 0xff00);
- outl(((on << 1) + 0x10), (pm10_bar + 0x10));
- inl(pm10_bar + 0x10);
- on = 8-on;
- printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
- (on * 12) + (on >> 1), (on & 1) * 5);
- }
-
-#if CONFIG(HAVE_ACPI_TABLES)
- pm_base = pci_read_config16(dev, 0x58) & 0xff00;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-#endif
-
-}
-
-static void acpi_read_resources(struct device *dev)
-{
- struct resource *resource;
-
- /* Handle the generic bars */
- pci_dev_read_resources(dev);
-
- /* Add the ACPI/SMBUS bar */
- resource = new_resource(dev, 0x58);
- resource->base = 0;
- resource->size = 256;
- resource->align = log2(256);
- resource->gran = log2(256);
- resource->limit = 65536;
- resource->flags = IORESOURCE_IO;
- resource->index = 0x58;
-}
-
-static void acpi_enable_resources(struct device *dev)
-{
- uint8_t byte;
- /* Enable the generic pci resources */
- pci_dev_enable_resources(dev);
-
- /* Enable the ACPI/SMBUS Bar */
- byte = pci_read_config8(dev, 0x41);
- byte |= (1 << 7);
- pci_write_config8(dev, 0x41, byte);
-
- /* Set the class code */
- pci_write_config32(dev, 0x60, 0x06800000);
-
-}
-
-static void lpci_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
-{
- pci_write_config32(dev, 0x7c,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
- .recv_byte = lsmbus_recv_byte,
- .send_byte = lsmbus_send_byte,
- .read_byte = lsmbus_read_byte,
- .write_byte = lsmbus_write_byte,
- .block_read = lsmbus_block_read,
- .block_write= lsmbus_block_write,
-};
-
-static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
-};
-
-static struct device_operations acpi_ops = {
- .read_resources = acpi_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = acpi_enable_resources,
- .init = acpi_init,
- .scan_bus = scan_smbus,
- /* We don't need amd8111_enable, chip ops takes care of it.
- * It could be useful if these devices were not
- * enabled by default.
- */
-// .enable = amd8111_enable,
- .ops_pci = &lops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
-};
-
-static const struct pci_driver acpi_driver __pci_driver = {
- .ops = &acpi_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8111_ACPI,
-};
diff --git a/src/southbridge/amd/amd8111/acpi/sleepstates.asl b/src/southbridge/amd/amd8111/acpi/sleepstates.asl
deleted file mode 100644
index 19fde4ded2..0000000000
--- a/src/southbridge/amd/amd8111/acpi/sleepstates.asl
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
-#if CONFIG(HAVE_ACPI_RESUME)
-Name (SSFG, 0x05)
-#else
-Name (SSFG, 0x01)
-#endif
-
-/* Supported sleep states: */
-Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
-
-If (And(SSFG, 0x01)) {
- Name(\_S1, Package () {0x01, 0x01, 0x01, 0x01} ) /* (S1) - sleeping w/CPU context */
-}
-If (And(SSFG, 0x02)) {
- Name(\_S2, Package () {0x02, 0x02, 0x02, 0x02} ) /* (S2) - "light" Suspend to RAM */
-}
-If (And(SSFG, 0x04)) {
- Name(\_S3, Package () {0x05, 0x05, 0x05, 0x05} ) /* (S3) - Suspend to RAM */
-}
-If (And(SSFG, 0x08)) {
- Name(\_S4, Package () {0x06, 0x06, 0x06, 0x06} ) /* (S4) - Suspend to Disk */
-}
-
-Name(\_S5, Package () {0x07, 0x07, 0x07, 0x07} ) /* (S5) - Soft Off */
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c
deleted file mode 100644
index 0180f45653..0000000000
--- a/src/southbridge/amd/amd8111/amd8111.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include "amd8111.h"
-
-void amd8111_enable(struct device *dev)
-{
- struct device *lpc_dev;
- struct device *bus_dev;
- unsigned int index;
- unsigned int reg_old, reg;
-
- /* See if we are on the bus behind the amd8111 pci bridge */
- bus_dev = dev->bus->dev;
- if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
- (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
- {
- unsigned int devfn;
- devfn = bus_dev->path.pci.devfn + (1 << 3);
- lpc_dev = pcidev_path_behind(bus_dev->bus, devfn);
- index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
- if (dev->path.pci.devfn == 2) { /* EHCI */
- index = 16;
- }
- } else {
- unsigned int devfn;
- devfn = (dev->path.pci.devfn) & ~7;
- lpc_dev = pcidev_path_behind(dev->bus, devfn);
- index = dev->path.pci.devfn & 7;
- }
- if ((!lpc_dev) || (index >= 17)) {
- return;
- }
- if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) ||
- (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA))
- {
- uint32_t id;
- id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
- if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) {
- return;
- }
- }
-
- if (index < 16) {
- reg = reg_old = pci_read_config16(lpc_dev, 0x48);
- reg &= ~(1 << index);
- if (dev->enabled) {
- reg |= (1 << index);
- }
- if (reg != reg_old) {
- pci_write_config16(lpc_dev, 0x48, reg);
- }
- }
- else if (index == 16) {
- reg = reg_old = pci_read_config8(lpc_dev, 0x47);
- reg &= ~(1 << 7);
- if (!dev->enabled) {
- reg |= (1 << 7);
- }
- if (reg != reg_old) {
- pci_write_config8(lpc_dev, 0x47, reg);
- }
- }
-}
-
-struct chip_operations southbridge_amd_amd8111_ops = {
- CHIP_NAME("AMD-8111 Southbridge")
- /* This only called when this device is listed in the
- * static device tree.
- */
- .enable_dev = amd8111_enable,
-};
diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h
deleted file mode 100644
index fc57936908..0000000000
--- a/src/southbridge/amd/amd8111/amd8111.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef AMD8111_H
-#define AMD8111_H
-
-#include <device/device.h>
-
-void amd8111_enable(struct device *dev);
-void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
-
-#endif /* AMD8111_H */
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
deleted file mode 100644
index 894fcd0a61..0000000000
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/smbus_def.h>
-
-#define SMBGSTATUS 0xe0
-#define SMBGCTL 0xe2
-#define SMBHSTADDR 0xe4
-#define SMBHSTDAT 0xe6
-#define SMBHSTCMD 0xe8
-#define SMBHSTFIFO 0xe9
-
-#define SMBUS_TIMEOUT (100*1000*10)
-#define SMBUS_STATUS_MASK 0xfbff
-
-static inline void smbus_delay(void)
-{
- outb(0x80, 0x80);
-}
-
-static int smbus_wait_until_ready(unsigned int smbus_io_base)
-{
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- do {
- unsigned short val;
- smbus_delay();
- val = inw(smbus_io_base + SMBGSTATUS);
- if ((val & 0x800) == 0) {
- break;
- }
- if (loops == (SMBUS_TIMEOUT / 2)) {
- outw(inw(smbus_io_base + SMBGSTATUS),
- smbus_io_base + SMBGSTATUS);
- }
- } while (--loops);
- return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_wait_until_done(unsigned int smbus_io_base)
-{
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- do {
- unsigned short val;
- smbus_delay();
-
- val = inw(smbus_io_base + SMBGSTATUS);
- if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
- break;
- }
- } while (--loops);
- return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
-}
-
-static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
-{
- unsigned int global_status_register;
- unsigned int byte;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
-
- /* setup transaction */
- /* disable interrupts */
- outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
- /* set the device I'm talking to */
- outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
- /* set the command/address... */
- outb(0, smbus_io_base + SMBHSTCMD);
- /* set up for a send byte */
- outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
-
- /* clear any lingering errors, so the transaction will run */
- /* Do I need to write the bits to a 1 to clear an error? */
- outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
-
- /* set the data word...*/
- outw(0, smbus_io_base + SMBHSTDAT);
-
- /* start the command */
- outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
-
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
-
- global_status_register = inw(smbus_io_base + SMBGSTATUS);
-
- /* read results of transaction */
- byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
-
- if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
- return SMBUS_ERROR;
- }
- return byte;
-}
-
-static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device,
- unsigned int value)
-{
- unsigned int global_status_register;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
-
- /* setup transaction */
- /* disable interrupts */
- outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
- /* set the device I'm talking to */
- outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
- /* set the command/address... */
- outb(0, smbus_io_base + SMBHSTCMD);
- /* set up for a send byte */
- outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL);
-
- /* clear any lingering errors, so the transaction will run */
- /* Do I need to write the bits to a 1 to clear an error? */
- outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
-
- /* set the data word...*/
- outw(value, smbus_io_base + SMBHSTDAT);
-
- /* start the command */
- outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
-
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
- global_status_register = inw(smbus_io_base + SMBGSTATUS);
-
- if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
- return SMBUS_ERROR;
- }
- return 0;
-}
-
-
-static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device,
- unsigned int address)
-{
- unsigned int global_status_register;
- unsigned int byte;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
-
- /* setup transaction */
- /* disable interrupts */
- outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
- /* set the device I'm talking to */
- outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
- /* set the command/address... */
- outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
- /* set up for a byte data read */
- outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL);
-
- /* clear any lingering errors, so the transaction will run */
- /* Do I need to write the bits to a 1 to clear an error? */
- outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
-
- /* clear the data word...*/
- outw(0, smbus_io_base + SMBHSTDAT);
-
- /* start the command */
- outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
-
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
-
- global_status_register = inw(smbus_io_base + SMBGSTATUS);
-
- /* read results of transaction */
- byte = inw(smbus_io_base + SMBHSTDAT) & 0xff;
-
- if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
- return SMBUS_ERROR;
- }
- return byte;
-}
-
-static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device,
- unsigned int address, unsigned char val)
-{
- unsigned int global_status_register;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
-
- /* setup transaction */
- /* disable interrupts */
- outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
- /* set the device I'm talking to */
- outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
- outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
- /* set up for a byte data write */ /* FIXME */
- outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL);
- /* clear any lingering errors, so the transaction will run */
- /* Do I need to write the bits to a 1 to clear an error? */
- outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
-
- /* write the data word...*/
- outw(val, smbus_io_base + SMBHSTDAT);
-
- /* start the command */
- outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
- global_status_register = inw(smbus_io_base + SMBGSTATUS);
-
- if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
- return SMBUS_ERROR;
- }
- return 0;
-}
-
-static int do_smbus_block_read(unsigned int smbus_io_base, unsigned int device,
- unsigned int cmd, u8 bytes, u8 *buf)
-{
- unsigned int global_status_register;
- unsigned int i;
- u8 msglen;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
-
- /* setup transaction */
- /* disable interrupts */
- outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
- /* set the device I'm talking to */
- outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
- /* set the command/address... */
- outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD);
- /* set up for a block data read */
- outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL);
-
- /* clear any lingering errors, so the transaction will run */
- /* Do I need to write the bits to a 1 to clear an error? */
- outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
-
- /* clear the length word...*/
- outw(0, smbus_io_base + SMBHSTDAT);
-
- /* start the command */
- outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
-
- global_status_register = inw(smbus_io_base + SMBGSTATUS);
-
- /* read results of transaction */
- msglen = inw(smbus_io_base + SMBHSTDAT) & 0x3f;
-
- if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
- return SMBUS_ERROR;
- }
-
- /* read data block */
- for (i = 0; i < msglen && i < bytes; i++) {
- buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff;
- }
- /* empty fifo */
- while (bytes++<msglen) {
- inw(smbus_io_base + SMBHSTFIFO);
- }
-
- return i;
-}
-
-static int do_smbus_block_write(unsigned int smbus_io_base, unsigned int device,
- unsigned int cmd, u8 bytes, const u8 *buf)
-{
- unsigned int global_status_register;
- unsigned int i;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
- }
-
- /* setup transaction */
- /* disable interrupts */
- outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
- /* set the device I'm talking to */
- outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
- /* set the command/address... */
- outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD);
- /* set up for a block data write */
- outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL);
-
- /* clear any lingering errors, so the transaction will run */
- /* Do I need to write the bits to a 1 to clear an error? */
- outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS);
-
- /* set the length word...*/
- outw(bytes, smbus_io_base + SMBHSTDAT);
-
- /* set the data block */
- for (i = 0; i < bytes; i++) {
- outw(buf[i], smbus_io_base + SMBHSTFIFO);
- }
-
- /* start the command */
- outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
- }
- global_status_register = inw(smbus_io_base + SMBGSTATUS);
-
- if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) {
- return SMBUS_ERROR;
- }
- return 0;
-}
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
deleted file mode 100644
index 40622bae75..0000000000
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Linux Networx
- * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <device/pci_type.h>
-
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \
- ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-
-static pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev)
-{
- for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
- unsigned int id;
- id = pci_io_read_config32(dev, 0);
- if (id == pci_id)
- return dev;
- }
- return PCI_DEV_INVALID;
-}
-
-/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */
-static void amd8111_enable_rom(void)
-{
- u8 byte;
- pci_devfn_t dev;
-
- dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD,
- PCI_DEVICE_ID_AMD_8111_ISA), 0);
-
- /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */
-
- /* Set the 5MB enable bits. */
- byte = pci_io_read_config8(dev, 0x43);
- byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */
- byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */
- pci_io_write_config8(dev, 0x43, byte);
-}
-
-static void bootblock_southbridge_init(void)
-{
- amd8111_enable_rom();
-}
diff --git a/src/southbridge/amd/amd8111/chip.h b/src/southbridge/amd/amd8111/chip.h
deleted file mode 100644
index 54501f5039..0000000000
--- a/src/southbridge/amd/amd8111/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef AMD8111_CHIP_H
-#define AMD8111_CHIP_H
-
-struct southbridge_amd_amd8111_config
-{
- unsigned int ide0_enable : 1;
- unsigned int ide1_enable : 1;
- unsigned int phy_lowreset : 1;
-};
-
-#endif /* AMD8111_CHIP_H */
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
deleted file mode 100644
index e9676ebc08..0000000000
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 yhlu
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pci_ids.h>
-#include <reset.h>
-#include <southbridge/amd/common/reset.h>
-#include "amd8111.h"
-
-unsigned int get_sbdn(unsigned int bus)
-{
- pci_devfn_t dev;
-
- /* Find the device.
- * There can only be one 8111 on a hypertransport chain/bus.
- */
- dev = pci_locate_device_on_bus(
- PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
- bus);
-
- return (dev>>15) & 0x1f;
-
-}
-
-static void enable_cf9_x(unsigned int sbbusn, unsigned int sbdn)
-{
- pci_devfn_t dev;
- uint8_t byte;
-
- dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI
- /* enable cf9 */
- byte = pci_read_config8(dev, 0x41);
- byte |= (1<<6) | (1<<5);
- pci_write_config8(dev, 0x41, byte);
-}
-
-static void enable_cf9(void)
-{
- unsigned int sblk = get_sblk();
- unsigned int sbbusn = get_sbbusn(sblk);
- unsigned int sbdn = get_sbdn(sbbusn);
-
- enable_cf9_x(sbbusn, sbdn);
-}
-
-void do_board_reset(void)
-{
- set_bios_reset();
- /* reset */
- enable_cf9();
- outb(0x0e, 0x0cf9); // make sure cf9 is enabled
-}
-
-void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
-{
- pci_devfn_t dev;
-
- dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
-
- pci_write_config8(dev, 0x74, 4);
-
- /* set VFSMAF (VID/FID System Management Action Field) to 2 */
- pci_write_config32(dev, 0x70, 2<<12);
-
-}
-
-static void soft_reset_x(unsigned int sbbusn, unsigned int sbdn)
-{
- pci_devfn_t dev;
-
- dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
-
- /* Reset */
- set_bios_reset();
- pci_write_config8(dev, 0x47, 1);
-
-}
-
-void do_soft_reset(void)
-{
-
- unsigned int sblk = get_sblk();
- unsigned int sbbusn = get_sbbusn(sblk);
- unsigned int sbdn = get_sbdn(sbbusn);
-
- return soft_reset_x(sbbusn, sbdn);
-
-}
diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c
deleted file mode 100644
index c82190223d..0000000000
--- a/src/southbridge/amd/amd8111/early_smbus.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/pci_ops.h>
-
-#include "amd8111_smbus.h"
-
-#define SMBUS_IO_BASE 0x0f00
-
-static void enable_smbus(void)
-{
- pci_devfn_t dev;
- uint8_t enable;
-
- dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
- if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\n");
- }
-
- pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
- enable = pci_read_config8(dev, 0x41);
- pci_write_config8(dev, 0x41, enable | (1 << 7));
-
- /* check that we can see the smbus controller I/O. */
- if (inw(SMBUS_IO_BASE)==0xFF){
- die("SMBUS controller I/O not found\n");
- }
-
- /* clear any lingering errors, so the transaction will run */
- outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
- printk(BIOS_SPEW, "SMBus controller enabled\n");
-}
-
-static inline int smbus_recv_byte(unsigned int device)
-{
- return do_smbus_recv_byte(SMBUS_IO_BASE, device);
-}
-
-static inline int smbus_send_byte(unsigned int device, unsigned char val)
-{
- return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
-}
-
-static inline int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-static inline int smbus_write_byte(unsigned int device, unsigned int address,
- unsigned char val)
-{
- return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
-}
-
-static inline int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes,
- u8 *buf)
-{
- return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
-}
-
-static inline int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
- const u8 *buf)
-{
- return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
-}
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c
deleted file mode 100644
index 49f9d154f8..0000000000
--- a/src/southbridge/amd/amd8111/ide.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "amd8111.h"
-#include "chip.h"
-
-static void ide_init(struct device *dev)
-{
- struct southbridge_amd_amd8111_config *conf;
- /* Enable ide devices so the linux ide driver will work */
- uint16_t word;
- uint8_t byte;
- conf = dev->chip_info;
-
- word = pci_read_config16(dev, 0x40);
- /* Ensure prefetch is disabled */
- word &= ~((1 << 15) | (1 << 13));
- if (conf->ide1_enable) {
- /* Enable secondary ide interface */
- word |= (1<<0);
- printk(BIOS_DEBUG, "IDE1 ");
- }
- if (conf->ide0_enable) {
- /* Enable primary ide interface */
- word |= (1<<1);
- printk(BIOS_DEBUG, "IDE0 ");
- }
-
- word |= (1<<12);
- word |= (1<<14);
-
- pci_write_config16(dev, 0x40, word);
-
-
- byte = 0x20; // Latency: 64-->32
- pci_write_config8(dev, 0xd, byte);
-
- word = 0x0f;
- pci_write_config16(dev, 0x42, word);
-}
-
-static void lpci_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
-{
- pci_write_config32(dev, 0x70,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
-};
-static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .scan_bus = 0,
- .enable = amd8111_enable,
- .ops_pci = &lops_pci
-};
-
-static const struct pci_driver ide_driver __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8111_IDE,
-};
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
deleted file mode 100644
index b4a92a0f03..0000000000
--- a/src/southbridge/amd/amd8111/lpc.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2003 Linux Networx, SuSE Linux AG
- * 2006.1 yhlu add dest apicid for IRQ0
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/isa-dma.h>
-#include <cpu/x86/lapic.h>
-#include <arch/ioapic.h>
-#if CONFIG(HAVE_ACPI_TABLES)
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <cpu/amd/powernow.h>
-#endif
-#include <stdlib.h>
-
-#include "amd8111.h"
-
-#define NMI_OFF 0
-
-static void enable_hpet(struct device *dev)
-{
- unsigned long hpet_address;
-
- pci_write_config32(dev, 0xa0, CONFIG_HPET_ADDRESS|1);
- hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
- printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
-
-}
-
-static void lpc_init(struct device *dev)
-{
- uint8_t byte;
- int nmi_option;
-
- /* IO APIC initialization */
- byte = pci_read_config8(dev, 0x4B);
- byte |= 1;
- pci_write_config8(dev, 0x4B, byte);
- /* Don't rename IO APIC */
- setup_ioapic(VIO_APIC_VADDR, 0);
-
- /* posted memory write enable */
- byte = pci_read_config8(dev, 0x46);
- pci_write_config8(dev, 0x46, byte | (1<<0));
-
- /* Enable 5Mib Rom window */
- byte = pci_read_config8(dev, 0x43);
- byte |= 0xc0;
- pci_write_config8(dev, 0x43, byte);
-
- /* Enable Port 92 fast reset */
- byte = pci_read_config8(dev, 0x41);
- byte |= (1 << 5);
- pci_write_config8(dev, 0x41, byte);
-
- /* Enable Error reporting */
- /* Set up sync flood detected */
- byte = pci_read_config8(dev, 0x47);
- byte |= (1 << 1);
- pci_write_config8(dev, 0x47, byte);
-
- /* Set up NMI on errors */
- byte = pci_read_config8(dev, 0x40);
- byte |= (1 << 1); /* clear PW2LPC error */
- byte |= (1 << 6); /* clear LPCERR */
- pci_write_config8(dev, 0x40, byte);
- nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
- if (nmi_option) {
- byte |= (1 << 7); /* set NMI */
- pci_write_config8(dev, 0x40, byte);
- }
-
- /* Initialize the real time clock */
- cmos_init(0);
-
- /* Initialize isa dma */
- isa_dma_init();
-
- /* Initialize the High Precision Event Timers */
- enable_hpet(dev);
-}
-
-static void amd8111_lpc_read_resources(struct device *dev)
-{
- struct resource *res;
-
- /* Get the normal PCI resources of this device. */
- pci_dev_read_resources(dev);
-
- /* Add an extra subtractive resource for both memory and I/O. */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->base = 0;
- res->size = 0x1000;
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->base = 0xff800000;
- res->size = 0x00800000; /* 8 MB for flash */
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = IO_APIC_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void lpci_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
-{
- pci_write_config32(dev, 0x70,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-#if CONFIG(HAVE_ACPI_TABLES)
-
-extern u16 pm_base;
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
- /* Just a dummy */
- return current;
-}
-
-static void southbridge_acpi_fill_ssdt_generator(struct device *device) {
-#if CONFIG(SET_FIDVID)
- amd_generate_powernow(pm_base + 0x10, 6, 1);
- acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
-#endif
-}
-
-#endif
-
-
-static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
-};
-
-static struct device_operations lpc_ops = {
- .read_resources = amd8111_lpc_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = lpc_init,
-#if CONFIG(HAVE_ACPI_TABLES)
- .write_acpi_tables = acpi_write_hpet,
- .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
-#endif
- .scan_bus = scan_static_bus,
- .enable = amd8111_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8111_ISA,
-};
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
deleted file mode 100644
index a4abd0360a..0000000000
--- a/src/southbridge/amd/amd8111/nic.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/mmio.h>
-#include <delay.h>
-#include "amd8111.h"
-#include "chip.h"
-
-#define CMD3 0x54
-
-typedef enum {
- VAL3 = (1 << 31), /* VAL bit for byte 3 */
- VAL2 = (1 << 23), /* VAL bit for byte 2 */
- VAL1 = (1 << 15), /* VAL bit for byte 1 */
- VAL0 = (1 << 7), /* VAL bit for byte 0 */
-}VAL_BITS;
-
-typedef enum {
- /* VAL3 */
- ASF_INIT_DONE_ALIAS = (1 << 29),
- /* VAL2 */
- JUMBO = (1 << 21),
- VSIZE = (1 << 20),
- VLONLY = (1 << 19),
- VL_TAG_DEL = (1 << 18),
- /* VAL1 */
- EN_PMGR = (1 << 14),
- INTLEVEL = (1 << 13),
- FORCE_FULL_DUPLEX = (1 << 12),
- FORCE_LINK_STATUS = (1 << 11),
- APEP = (1 << 10),
- MPPLBA = (1 << 9),
- /* VAL0 */
- RESET_PHY_PULSE = (1 << 2),
- RESET_PHY = (1 << 1),
- PHY_RST_POL = (1 << 0),
-}CMD3_BITS;
-
-static void nic_init(struct device *dev)
-{
- struct southbridge_amd_amd8111_config *conf;
- struct resource *resource;
- u8 *mmio;
-
- conf = dev->chip_info;
- resource = find_resource(dev, PCI_BASE_ADDRESS_0);
- mmio = res2mmio(resource, 0, 0);
-
- /* Hard Reset PHY */
- printk(BIOS_DEBUG, "Resetting PHY... ");
- if (conf->phy_lowreset) {
- write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
- } else {
- write32((mmio + CMD3), VAL0 | RESET_PHY);
- }
- mdelay(15);
- write32((mmio + CMD3), RESET_PHY);
- printk(BIOS_DEBUG, "Done\n");
-}
-
-static void lpci_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
-{
- pci_write_config32(dev, 0xc8,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
-};
-
-static struct device_operations nic_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = nic_init,
- .scan_bus = 0,
- .enable = amd8111_enable,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver nic_driver __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8111_NIC,
-};
diff --git a/src/southbridge/amd/amd8111/pci.c b/src/southbridge/amd/amd8111/pci.c
deleted file mode 100644
index ae47716627..0000000000
--- a/src/southbridge/amd/amd8111/pci.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "amd8111.h"
-
-static void pci_init(struct device *dev)
-{
-
- /* Enable pci error detecting */
- uint32_t dword;
-
- /* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* System error enable */
- dword |= (7<<28); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
-
- /* System,Parity,timer,and abort error enable */
- dword = pci_read_config32(dev, 0x3c);
- dword |= (1<<16); /* Parity */
- dword |= (1<<17); /* System */
- dword |= (1<<21); /* Master abort */
-// dword &= ~(1<<21); /* Master abort */
-// dword |= (1<<27); /* Discard timer */
- dword &= ~(1<<27); /* Discard timer */
- dword |= (1<<26); /* DTSTAT error clear */
- pci_write_config32(dev, 0x3c, dword);
-
- /* CRC flood enable */
- dword = pci_read_config32(dev, 0xc4);
- dword |= (1<<1); /* CRC Flood enable */
- dword |= (1<<8); /* Clear any CRC errors */
- dword |= (1<<4); /* Clear any LKFAIL errors */
- pci_write_config32(dev, 0xc4, dword);
-
- /* Clear possible errors */
- dword = pci_read_config32(dev, 0x1c);
- dword |= (1<<27); /* STA */
- dword |= (1<<28); /* RTA */
- dword |= (1<<29); /* RMA */
- dword |= (1<<30); /* RSE */
- dword |= (1<<31); /* DPE */
- dword |= (1<<24); /* MDPE */
- pci_write_config32(dev, 0x1c, dword);
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = 0,
-};
-
-static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pci_init,
- .scan_bus = pci_scan_bridge,
- /* PCI Subordinate bus reset is not implemented */
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8111_PCI,
-};
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
deleted file mode 100644
index b175be2727..0000000000
--- a/src/southbridge/amd/amd8111/reset.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#define __SIMPLE_DEVICE__
-
-#include <device/pci_ops.h>
-#include <reset.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-
-#define PCI_DEV_INVALID (0xffffffffU)
-static pci_devfn_t pci_io_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
-{
- pci_devfn_t dev, last;
- dev = PCI_DEV(bus, 0, 0);
- last = PCI_DEV(bus, 31, 7);
- for (; dev <= last; dev += PCI_DEV(0,0,1)) {
- unsigned int id;
- id = pci_io_read_config32(dev, 0);
- if (id == pci_id) {
- return dev;
- }
- }
- return PCI_DEV_INVALID;
-}
-
-#include "../../../northbridge/amd/amdk8/reset_test.c"
-
-void do_board_reset(void)
-{
- pci_devfn_t dev;
- unsigned int bus;
- unsigned int node = 0;
- unsigned int link = get_sblk();
-
- /* Find the device.
- * There can only be one 8111 on a hypertransport chain/bus.
- */
- bus = node_link_to_bus(node, link);
- dev = pci_io_locate_device_on_bus(
- PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
- bus);
-
- /* Reset */
- set_bios_reset();
- pci_io_write_config8(dev, 0x47, 1);
-}
diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c
deleted file mode 100644
index aa580fecbb..0000000000
--- a/src/southbridge/amd/amd8111/smbus.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/smbus.h>
-#include "amd8111.h"
-
-
-static void lpci_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
-{
- pci_write_config32(dev, 0x44,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
- /* I haven't seen the 2.0 SMBUS controller used yet. */
-};
-static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
-};
-static struct device_operations smbus_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = scan_smbus,
- .enable = amd8111_enable,
- .ops_pci = &lops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
-};
-
-static const struct pci_driver smbus_driver __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8111_SMB,
-};
diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c
deleted file mode 100644
index 741cad9d37..0000000000
--- a/src/southbridge/amd/amd8111/usb.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * (C) 2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "amd8111.h"
-
-
-static void lpci_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
-{
- pci_write_config32(dev, 0x70,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
-};
-
-static struct device_operations usb_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver usb_driver __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8111_USB,
-};
diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c
deleted file mode 100644
index b41c0bee66..0000000000
--- a/src/southbridge/amd/amd8111/usb2.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2003 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "amd8111.h"
-
-static void amd8111_usb2_enable(struct device *dev)
-{
- // Due to buggy USB2 we force it to disable.
- dev->enabled = 0;
- amd8111_enable(dev);
- printk(BIOS_DEBUG, "USB2 disabled.\n");
-}
-
-static struct device_operations usb2_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .scan_bus = 0,
- .enable = amd8111_usb2_enable,
-};
-
-static const struct pci_driver usb2_driver __pci_driver = {
- .ops = &usb2_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_8111_USB2,
-};
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 13:28:31 +0000