diff options
Diffstat (limited to 'src/southbridge/intel/bd82x6x/lpc.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 19 |
1 files changed, 2 insertions, 17 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 271b5b06cc..67f1de6a07 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -27,7 +27,6 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> -#include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> #include <cpu/x86/smm.h> @@ -39,6 +38,7 @@ #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/rtc.h> #define NMI_OFF 0 @@ -279,21 +279,6 @@ static void pch_power_options(struct device *dev) RCBA32(0x3f02) = reg32; } -static void pch_rtc_init(struct device *dev) -{ - int rtc_failed = rtc_failure(); - - if (rtc_failed) { - if (IS_ENABLED(CONFIG_ELOG)) - elog_add_event(ELOG_TYPE_RTC_RESET); - pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0); - } - - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - - cmos_init(rtc_failed); -} - /* CougarPoint PCH Power Management init */ static void cpt_pm_init(struct device *dev) { @@ -605,7 +590,7 @@ static void lpc_init(struct device *dev) //gpio_init(dev); /* Initialize the real time clock. */ - pch_rtc_init(dev); + sb_rtc_init(); /* Initialize ISA DMA. */ isa_dma_init(); |