summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x/lpc.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/bd82x6x/lpc.c')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 3bdefc4d74..17f824c87d 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -51,6 +51,10 @@ static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
+ /* Assign unique bus/dev/fn for I/O APIC */
+ pci_write_config16(dev, LPC_IBDF,
+ PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
+
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
@@ -375,9 +379,15 @@ static void ppt_pm_init(struct device *dev)
RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
}
-static void enable_hpet(void)
+static void enable_hpet(struct device *const dev)
{
u32 reg32;
+ size_t i;
+
+ /* Assign unique bus/dev/fn for each HPET */
+ for (i = 0; i < 8; ++i)
+ pci_write_config16(dev, LPC_HnBDF(i),
+ PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
/* Move HPET to default address 0xfed00000 and enable it */
reg32 = RCBA32(HPTC);
@@ -531,7 +541,7 @@ static void lpc_init(struct device *dev)
isa_dma_init();
/* Initialize the High Precision Event Timers, if present. */
- enable_hpet();
+ enable_hpet(dev);
/* Initialize Clock Gating */
enable_clock_gating(dev);