1 files changed, 61 insertions, 47 deletions

diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 7e1a3bc19c..0cb64964cf 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -47,30 +47,36 @@
 #define  ME_HFS_ACK_GBL_RESET	6
 #define  ME_HFS_ACK_CONTINUE	7
 
-struct me_hfs {
-	u32 working_state: 4;
-	u32 mfg_mode: 1;
-	u32 fpt_bad: 1;
-	u32 operation_state: 3;
-	u32 fw_init_complete: 1;
-	u32 ft_bup_ld_flr: 1;
-	u32 update_in_progress: 1;
-	u32 error_code: 4;
-	u32 operation_mode: 4;
-	u32 reserved: 4;
-	u32 boot_options_present: 1;
-	u32 ack_data: 3;
-	u32 bios_msg_ack: 4;
+union me_hfs {
+	struct {
+		u32 working_state: 4;
+		u32 mfg_mode: 1;
+		u32 fpt_bad: 1;
+		u32 operation_state: 3;
+		u32 fw_init_complete: 1;
+		u32 ft_bup_ld_flr: 1;
+		u32 update_in_progress: 1;
+		u32 error_code: 4;
+		u32 operation_mode: 4;
+		u32 reserved: 4;
+		u32 boot_options_present: 1;
+		u32 ack_data: 3;
+		u32 bios_msg_ack: 4;
+	};
+	u32 raw;
 } __packed;
 
 #define PCI_ME_UMA		0x44
 
-struct me_uma {
-	u32 size: 6;
-	u32 reserved_1: 10;
-	u32 valid: 1;
-	u32 reserved_0: 14;
-	u32 set_to_one: 1;
+union me_uma {
+	struct {
+		u32 size: 6;
+		u32 reserved_1: 10;
+		u32 valid: 1;
+		u32 reserved_0: 14;
+		u32 set_to_one: 1;
+	};
+	u32 raw;
 } __packed;
 
 #define PCI_ME_H_GS		0x4c
@@ -79,11 +85,14 @@ struct me_uma {
 #define  ME_INIT_STATUS_NOMEM	1
 #define  ME_INIT_STATUS_ERROR	2
 
-struct me_did {
-	u32 uma_base: 16;
-	u32 reserved: 8;
-	u32 status: 4;
-	u32 init_done: 4;
+union me_did {
+	struct {
+		u32 uma_base: 16;
+		u32 reserved: 8;
+		u32 status: 4;
+		u32 init_done: 4;
+	};
+	u32 raw;
 } __packed;
 
 #define PCI_ME_GMES		0x48
@@ -95,21 +104,24 @@ struct me_did {
 #define  ME_GMES_PHASE_UNKNOWN	5
 #define  ME_GMES_PHASE_HOST	6
 
-struct me_gmes {
-	u32 bist_in_prog : 1;
-	u32 icc_prog_sts : 2;
-	u32 invoke_mebx : 1;
-	u32 cpu_replaced_sts : 1;
-	u32 mbp_rdy : 1;
-	u32 mfs_failure : 1;
-	u32 warm_rst_req_for_df : 1;
-	u32 cpu_replaced_valid : 1;
-	u32 reserved_1 : 2;
-	u32 fw_upd_ipu : 1;
-	u32 reserved_2 : 4;
-	u32 current_state: 8;
-	u32 current_pmevent: 4;
-	u32 progress_code: 4;
+union me_gmes {
+	struct {
+		u32 bist_in_prog : 1;
+		u32 icc_prog_sts : 2;
+		u32 invoke_mebx : 1;
+		u32 cpu_replaced_sts : 1;
+		u32 mbp_rdy : 1;
+		u32 mfs_failure : 1;
+		u32 warm_rst_req_for_df : 1;
+		u32 cpu_replaced_valid : 1;
+		u32 reserved_1 : 2;
+		u32 fw_upd_ipu : 1;
+		u32 reserved_2 : 4;
+		u32 current_state: 8;
+		u32 current_pmevent: 4;
+		u32 progress_code: 4;
+	};
+	u32 raw;
 } __packed;
 
 #define PCI_ME_HERES		0xbc
@@ -117,11 +129,14 @@ struct me_gmes {
 #define  PCI_ME_EXT_SHA256	0x02
 #define PCI_ME_HER(x)		(0xc0+(4*(x)))
 
-struct me_heres {
-	u32 extend_reg_algorithm: 4;
-	u32 reserved: 26;
-	u32 extend_feature_present: 1;
-	u32 extend_reg_valid: 1;
+union me_heres {
+	struct {
+		u32 extend_reg_algorithm: 4;
+		u32 reserved: 26;
+		u32 extend_feature_present: 1;
+		u32 extend_reg_valid: 1;
+	};
+	u32 raw;
 } __packed;
 
 /*
@@ -243,7 +258,6 @@ void mei_read_dword_ptr(void *ptr, int offset);
 void mei_write_dword_ptr(void *ptr, int offset);
 
 #ifndef __SIMPLE_DEVICE__
-void pci_read_dword_ptr(struct device *dev, void *ptr, int offset);
 bool enter_soft_temp_disable(void);
 void enter_soft_temp_disable_wait(void);
 void exit_soft_temp_disable(struct device *dev);
@@ -268,7 +282,7 @@ int intel_me_extend_valid(struct device *dev);
 void intel_me_hide(struct device *dev);
 
 /* Defined in me_status.c for both romstage and ramstage */
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
+void intel_me_status(union me_hfs *hfs, union me_gmes *gmes);
 
 void intel_early_me_status(void);
 int intel_early_me_init(void);