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Diffstat (limited to 'src/southbridge/intel/bd82x6x/pci.c')
-rw-r--r--src/southbridge/intel/bd82x6x/pci.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index a222893d88..833512a5b7 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "pch.h"
@@ -36,10 +37,10 @@ static void pci_init(struct device *dev)
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
- reg16 &= ~(1 << 0);
- reg16 &= ~(1 << 1);
- pci_write_config16(dev, BCTRL, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 &= ~PCI_BRIDGE_CTL_SERR;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);