summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/bd82x6x/Makefile.inc2
-rw-r--r--src/southbridge/intel/bd82x6x/include/soc/nvs.h (renamed from src/southbridge/intel/bd82x6x/nvs.h)0
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c12
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c2
5 files changed, 5 insertions, 12 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 3b05a3e678..06ac5c6455 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -11,6 +11,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select ACPI_SOC_NVS
select AZALIA_PLUGIN_SUPPORT
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 687fc97d4c..a591aabea0 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -38,4 +38,6 @@ else
romstage-y += early_me_mrc.c early_usb_mrc.c
endif
+CPPFLAGS_common += -I$(src)/southbridge/intel/bd82x6x/include
+
endif
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
index 949467b61c..949467b61c 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 73946d29bc..c2e7a86f09 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -18,13 +18,13 @@
#include <string.h>
#include "chip.h"
#include "pch.h"
-#include "nvs.h"
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/rtc.h>
#include <southbridge/intel/common/spi.h>
+#include <soc/nvs.h>
#define NMI_OFF 0
@@ -641,16 +641,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev);
}
-size_t gnvs_size_of_array(void)
-{
- return sizeof(struct global_nvs);
-}
-
-void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
-{
- return &gnvs->chromeos;
-}
-
void soc_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 3b37b06f83..bef98fae10 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -9,6 +9,7 @@
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <soc/nvs.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <southbridge/intel/common/gpio.h>
#include <cpu/intel/model_206ax/model_206ax.h>
@@ -16,7 +17,6 @@
#include <southbridge/intel/common/finalize.h>
#include "pch.h"
-#include "nvs.h"
int southbridge_io_trap_handler(int smif)
{