diff options
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/early_smbus.c | 33 | ||||
| -rw-r--r-- | src/southbridge/intel/common/early_smbus.h | 18 |
4 files changed, 56 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 195e71579c..3030d25757 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n +config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_SMBUS def_bool n select HAVE_DEBUG_SMBUS diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b3c48fa99c..1ededd23ec 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -5,6 +5,8 @@ subdirs-y += firmware all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/early_smbus.c b/src/southbridge/intel/common/early_smbus.c new file mode 100644 index 0000000000..d65b4aaf81 --- /dev/null +++ b/src/southbridge/intel/common/early_smbus.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/smbus_host.h> +#include "early_smbus.h" + +uintptr_t smbus_base(void) +{ + return CONFIG_FIXED_SMBUS_IO_BASE; +} + +int smbus_enable_iobar(uintptr_t base) +{ + /* Set the SMBus device statically. */ + const pci_devfn_t dev = PCI_DEV_SMBUS; + + /* Check to make sure we've got the right device. */ + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) + return -1; + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + return 0; +} diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h new file mode 100644 index 0000000000..d6a7cbbcce --- /dev/null +++ b/src/southbridge/intel/common/early_smbus.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H + +#include <device/pci_def.h> + +#define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3) + +#define SMB_BASE PCI_BASE_ADDRESS_4 +#define HOSTC 0x40 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +#endif /* SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H */ |