4 files changed, 90 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 4df559e38d..b87354c5e8 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -54,4 +54,9 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c
 
 ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c
 
+romstage-y += rtc.c
+ramstage-y += rtc.c
+postcar-y += rtc.c
+smm-y += rtc.c
+
 endif
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index 26134d9fad..c578982e92 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -21,6 +21,9 @@
 
 #define D31F0_PMBASE		0x40
 #define D31F0_GEN_PMCON_3	0xa4
+#define   RTC_BATTERY_DEAD		(1 << 2)
+#define   RTC_POWER_FAILED		(1 << 1)
+#define   SLEEP_AFTER_POWER_FAIL	(1 << 0)
 #define D31F0_GPIO_ROUT		0xb8
 #define  GPI_DISABLE		0x00
 #define  GPI_IS_SMI		0x01
diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c
new file mode 100644
index 0000000000..e9ac2c2deb
--- /dev/null
+++ b/src/southbridge/intel/common/rtc.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <security/vboot/vbnv.h>
+#include <pc80/mc146818rtc.h>
+#include <elog.h>
+#include "pmutil.h"
+#include "rtc.h"
+
+/* PCI Configuration Space (D31:F0): LPC */
+#if defined(__SIMPLE_DEVICE__)
+#define PCH_LPC_DEV	PCI_DEV(0, 0x1f, 0)
+#else
+#define PCH_LPC_DEV	dev_find_slot(0, PCI_DEVFN(0x1f, 0))
+#endif
+
+int rtc_failure(void)
+{
+	return !!(pci_read_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3)
+		  & RTC_BATTERY_DEAD);
+}
+
+void sb_rtc_init(void)
+{
+	int rtc_failed = rtc_failure();
+
+	if (rtc_failed) {
+		if (IS_ENABLED(CONFIG_ELOG))
+			elog_add_event(ELOG_TYPE_RTC_RESET);
+		pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3,
+				   ~RTC_BATTERY_DEAD, 0);
+	}
+
+	printk(BIOS_DEBUG, "RTC: failed = 0x%x\n", rtc_failed);
+
+	cmos_init(rtc_failed);
+}
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failure();
+}
diff --git a/src/southbridge/intel/common/rtc.h b/src/southbridge/intel/common/rtc.h
new file mode 100644
index 0000000000..0d04a51b5e
--- /dev/null
+++ b/src/southbridge/intel/common/rtc.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_RTC_H
+#define SOUTHBRIDGE_INTEL_RTC_H
+
+/* Return non-zero when RTC failure happened. */
+int rtc_failure(void);
+void sb_rtc_init(void);
+
+#endif