diff options
Diffstat (limited to 'src/southbridge/intel/common')
| -rw-r--r-- | src/southbridge/intel/common/finalize.c | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/common/pmutil.h | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/common/rtc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/smbus.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/common/smi.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/common/smihandler.c | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/common/spi.c | 12 | ||||
| -rw-r--r-- | src/southbridge/intel/common/usb_debug.c | 2 |
8 files changed, 27 insertions, 27 deletions
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index f1c33b9b06..80c65bb028 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -28,11 +28,11 @@ void intel_pch_finalize_smm(void) { const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) || - IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) { + if (CONFIG(LOCK_SPI_FLASH_RO) || + CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { int i; u32 lockmask = 1UL << 31; - if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) + if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) lockmask |= 1 << 15; for (i = 0; i < 20; i += 4) RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; @@ -41,7 +41,7 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); - if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ spi_init(); @@ -61,7 +61,7 @@ void intel_pch_finalize_smm(void) pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)) + if (CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)) /* PMSYNC */ RCBA32_OR(0x33c4, (1UL << 31)); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 7f07a724a3..eb74aa57ce 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -69,13 +69,13 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 #else #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */ +#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */ #define USB4_STS (1 << 14) /* i82801gx only */ #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -86,11 +86,11 @@ #define TCOSCI_STS (1 << 6) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #define GPE0_EN 0x2c #else #define GPE0_EN 0x28 -#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */ +#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */ #define PME_B0_EN (1 << 13) #define PME_EN (1 << 11) #define TCOSCI_EN (1 << 6) diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index 1f0abeb450..3ee12aa169 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -41,7 +41,7 @@ void sb_rtc_init(void) int rtc_failed = rtc_failure(); if (rtc_failed) { - if (IS_ENABLED(CONFIG_ELOG)) + if (CONFIG(ELOG)) elog_add_event(ELOG_TYPE_RTC_RESET); pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0); diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 9ae01ad178..4b08c48f27 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -22,7 +22,7 @@ #include "smbus.h" -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) +#if CONFIG(DEBUG_SMBUS) #define dprintk(args...) printk(BIOS_DEBUG, ##args) #else #define dprintk(args...) do {} while (0) @@ -369,8 +369,8 @@ int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd, /* Only since ICH5 */ static int has_i2c_read_command(void) { - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) || - IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || + CONFIG(SOUTHBRIDGE_INTEL_I82801DX)) return 0; return 1; } diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 40f5412a91..036ac22adc 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -40,7 +40,7 @@ void southbridge_smm_init(void) u16 pm1_en; u32 gpe0_en; - if (IS_ENABLED(CONFIG_ELOG)) + if (CONFIG(ELOG)) /* Log events from chipset before clearing */ pch_log_state(); @@ -159,7 +159,7 @@ void southbridge_smm_clear_state(void) { u32 smi_en; - if (IS_ENABLED(CONFIG_ELOG)) + if (CONFIG(ELOG)) /* Log events from chipset before clearing */ pch_log_state(); diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 05b73f20c3..b2cf49a45e 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -136,7 +136,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -244,7 +244,7 @@ em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -316,7 +316,7 @@ static void southbridge_smi_apmc(void) southbridge_finalize_all(); mainboard_finalized = 1; break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -340,7 +340,7 @@ static void southbridge_smi_pm1(void) // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif write_pmbase32(PM1_CNT, reg32); @@ -478,7 +478,7 @@ static smi_handler_t southbridge_smi[32] = { * @param node * @param state_save */ -#if IS_ENABLED(CONFIG_SMM_TSEG) +#if CONFIG(SMM_TSEG) void southbridge_smi_handler(void) #else void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a030ff4ef5..bf2a44c86c 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -161,7 +161,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +#if CONFIG(DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { @@ -283,7 +283,7 @@ void spi_init(void) rcba = pci_read_config32(dev, 0xf0); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020); cntlr->opmenu = ich7_spi->opmenu; cntlr->menubytes = sizeof(ich7_spi->opmenu); @@ -906,7 +906,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, { ich_spi_controller *cntlr = &g_cntlr; - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return spi_flash_generic_probe(spi, flash); /* Try generic probing first if spi_is_multichip returns 0. */ @@ -963,7 +963,7 @@ static u32 spi_fpr(u32 base, u32 limit) u32 ret; u32 mask, limit_shift; - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { mask = ICH7_SPI_FPR_MASK; limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT; } else { @@ -1011,12 +1011,12 @@ static int spi_flash_protect(const struct spi_flash *flash, protect_mask |= SPI_FPR_WPE; break; case READ_PROTECT: - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return -1; protect_mask |= ICH9_SPI_FPR_RPE; break; case READ_WRITE_PROTECT: - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) return -1; protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE); break; diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 4c5fe96b0d..d60264a15b 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -26,7 +26,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) u32 class; pci_devfn_t dev; - if (!IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)) + if (!CONFIG(HAVE_USBDEBUG_OPTIONS)) return PCI_DEV(0, 0x1d, 7); if (hcd_idx == 2) |