2 files changed, 27 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index e2b6e5828d..4aa2812ff1 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -123,5 +123,6 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done);
 void southbridge_finalize_all(void);
 void southbridge_smi_monitor(void);
 em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd);
+void pch_log_state(void);
 
 #endif /*INTEL_COMMON_PMUTIL_H */
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index deaecb2625..264b5487d8 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -159,3 +159,29 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 		  "d" (APM_CNT)
 	);
 }
+
+void southbridge_smm_clear_state(void)
+{
+	u32 smi_en;
+
+	if (IS_ENABLED(CONFIG_ELOG))
+	/* Log events from chipset before clearing */
+		pch_log_state();
+
+	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
+
+	smi_en = inl(get_pmbase() + SMI_EN);
+	if (smi_en & APMC_EN) {
+		printk(BIOS_INFO, "SMI# handler already enabled?\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "\n");
+
+	/* Dump and clear status registers */
+	reset_smi_status();
+	reset_pm1_status();
+	reset_tco_status();
+	reset_gpe0_status();
+}