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-rw-r--r--src/southbridge/intel/esb6300/chip.h2
-rw-r--r--src/southbridge/intel/esb6300/esb6300.c4
-rw-r--r--src/southbridge/intel/esb6300/esb6300_ac97.c2
-rw-r--r--src/southbridge/intel/esb6300/esb6300_early_smbus.c26
-rw-r--r--src/southbridge/intel/esb6300/esb6300_ehci.c4
-rw-r--r--src/southbridge/intel/esb6300/esb6300_ide.c4
-rw-r--r--src/southbridge/intel/esb6300/esb6300_lpc.c14
-rw-r--r--src/southbridge/intel/esb6300/esb6300_pic.c2
-rw-r--r--src/southbridge/intel/esb6300/esb6300_sata.c18
-rw-r--r--src/southbridge/intel/esb6300/esb6300_smbus.h2
-rw-r--r--src/southbridge/intel/esb6300/esb6300_uhci.c2
11 files changed, 40 insertions, 40 deletions
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h
index ff74e615fd..4082769cce 100644
--- a/src/southbridge/intel/esb6300/chip.h
+++ b/src/southbridge/intel/esb6300/chip.h
@@ -1,4 +1,4 @@
-struct southbridge_intel_esb6300_config
+struct southbridge_intel_esb6300_config
{
#define ESB6300_GPIO_USE_MASK 0x03
#define ESB6300_GPIO_USE_DEFAULT 0x00
diff --git a/src/southbridge/intel/esb6300/esb6300.c b/src/southbridge/intel/esb6300/esb6300.c
index 786daea23b..5d8f5e412d 100644
--- a/src/southbridge/intel/esb6300/esb6300.c
+++ b/src/southbridge/intel/esb6300/esb6300.c
@@ -25,7 +25,7 @@ void esb6300_enable(device_t dev)
(lpc_dev->device != PCI_DEVICE_ID_INTEL_6300ESB_LPC)) {
uint32_t id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
- if (id != (PCI_VENDOR_ID_INTEL |
+ if (id != (PCI_VENDOR_ID_INTEL |
(PCI_DEVICE_ID_INTEL_6300ESB_LPC << 16))) {
return;
}
@@ -39,7 +39,7 @@ void esb6300_enable(device_t dev)
if (reg != reg_old) {
pci_write_config16(lpc_dev, 0xf2, reg);
}
-
+
}
struct chip_operations southbridge_intel_esb6300_ops = {
diff --git a/src/southbridge/intel/esb6300/esb6300_ac97.c b/src/southbridge/intel/esb6300/esb6300_ac97.c
index 231f8129ad..7b7795f5df 100644
--- a/src/southbridge/intel/esb6300/esb6300_ac97.c
+++ b/src/southbridge/intel/esb6300/esb6300_ac97.c
@@ -8,7 +8,7 @@
static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* Write the subsystem vendor and device id */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/intel/esb6300/esb6300_early_smbus.c b/src/southbridge/intel/esb6300/esb6300_early_smbus.c
index ae7cfcd227..d804fde038 100644
--- a/src/southbridge/intel/esb6300/esb6300_early_smbus.c
+++ b/src/southbridge/intel/esb6300/esb6300_early_smbus.c
@@ -12,7 +12,7 @@ static void enable_smbus(void)
pci_write_config8(dev, 0x4, 1);
/* SMBALERT_DIS */
pci_write_config8(dev, 0x11, 4);
-
+
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
}
@@ -30,7 +30,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
return;
}
-static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
+static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
unsigned data1, unsigned data2)
{
unsigned char global_control_register;
@@ -41,11 +41,11 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
/* chear the PM timeout flags, SECOND_TO_STS */
outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
-
+
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
return -2;
}
-
+
/* setup transaction */
/* Obtain ownership */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
@@ -56,39 +56,39 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-
+
/* set the device I'm talking too */
outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-
+
/* set the command address */
outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-
+
/* set the block length */
outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
-
+
/* try sending out the first byte of data here */
byte=(data1>>(0))&0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
/* issue a block write command */
- outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
+ outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
SMBUS_IO_BASE + SMBHSTCTL);
for(i=0;i<length;i++) {
-
+
/* poll for transaction completion */
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
return -3;
}
-
+
/* load the next byte */
if(i>3)
byte=(data2>>(i%4))&0x0ff;
else
byte=(data1>>(i))&0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
-
+
/* clear the done bit */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
SMBUS_IO_BASE + SMBHSTSTAT);
}
diff --git a/src/southbridge/intel/esb6300/esb6300_ehci.c b/src/southbridge/intel/esb6300/esb6300_ehci.c
index 8c20c0325f..c103c4bd2f 100644
--- a/src/southbridge/intel/esb6300/esb6300_ehci.c
+++ b/src/southbridge/intel/esb6300/esb6300_ehci.c
@@ -11,7 +11,7 @@ static void ehci_init(struct device *dev)
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
+ pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_MASTER);
printk(BIOS_DEBUG, "done.\n");
@@ -24,7 +24,7 @@ static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
/* Enable writes to protected registers */
pci_write_config8(dev, 0x80, access_cntl | 1);
/* Write the subsystem vendor and device id */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
/* Restore protection */
pci_write_config8(dev, 0x80, access_cntl);
diff --git a/src/southbridge/intel/esb6300/esb6300_ide.c b/src/southbridge/intel/esb6300/esb6300_ide.c
index 543468dabb..abe86a811d 100644
--- a/src/southbridge/intel/esb6300/esb6300_ide.c
+++ b/src/southbridge/intel/esb6300/esb6300_ide.c
@@ -16,7 +16,7 @@ static void ide_init(struct device *dev)
pci_write_config8(dev, 0x48, 0x05);
pci_write_config16(dev, 0x4a, 0x0101);
pci_write_config16(dev, 0x54, 0x5055);
-
+
#if 0
uint16_t word;
word = pci_read_config16(dev, 0x40);
@@ -32,7 +32,7 @@ static void ide_init(struct device *dev)
static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* This value is also visible in uchi[0-2] and smbus functions */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c
index fe035bb2c4..66ac62bb3f 100644
--- a/src/southbridge/intel/esb6300/esb6300_lpc.c
+++ b/src/southbridge/intel/esb6300/esb6300_lpc.c
@@ -96,7 +96,7 @@ static void set_esb6300_gpio_direction(
switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) {
case ESB6300_GPIO_SEL_OUTPUT: val = 0; break;
case ESB6300_GPIO_SEL_INPUT: val = 1; break;
- default:
+ default:
continue;
}
/* The caller is responsible for not playing with unimplemented bits */
@@ -133,7 +133,7 @@ static void set_esb6300_gpio_level(
case ESB6300_GPIO_LVL_LOW: val = 0; blink = 0; break;
case ESB6300_GPIO_LVL_HIGH: val = 1; blink = 0; break;
case ESB6300_GPIO_LVL_BLINK: val = 1; blink = 1; break;
- default:
+ default:
continue;
}
/* The caller is responsible for not playing with unimplemented bits */
@@ -166,7 +166,7 @@ static void set_esb6300_gpio_inv(
switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) {
case ESB6300_GPIO_INV_OFF: val = 0; break;
case ESB6300_GPIO_INV_ON: val = 1; break;
- default:
+ default:
continue;
}
gpio_inv &= ~( 1 << i);
@@ -210,7 +210,7 @@ static void esb6300_gpio_init(device_t dev)
/* Find the GPIO bar */
res = find_resource(dev, GPIO_BAR);
if (!res) {
- return;
+ return;
}
/* Set the use selects */
@@ -274,7 +274,7 @@ static void lpc_init(struct device *dev)
pci_write_config8(dev, 0xa0, 0x20);
pci_write_config8(dev, 0xad, 0x03);
pci_write_config8(dev, 0xbb, 0x09);
-
+
esb6300_enable_serial_irqs(dev);
esb6300_pci_dma_cfg(dev);
@@ -292,7 +292,7 @@ static void lpc_init(struct device *dev)
/* Set up the PIRQ */
esb6300_pirq_init(dev);
-
+
/* Set the state of the gpio lines */
esb6300_gpio_init(dev);
@@ -346,7 +346,7 @@ static void esb6300_lpc_enable_resources(device_t dev)
acpi_cntl = pci_read_config8(dev, 0x44);
acpi_cntl |= (1 << 4);
pci_write_config8(dev, 0x44, acpi_cntl);
-
+
/* Enable the GPIO bar */
gpio_cntl = pci_read_config8(dev, 0x5c);
gpio_cntl |= (1 << 4);
diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c
index 9d02536cd4..5bbf317411 100644
--- a/src/southbridge/intel/esb6300/esb6300_pic.c
+++ b/src/southbridge/intel/esb6300/esb6300_pic.c
@@ -40,7 +40,7 @@ static void pic_read_resources(device_t dev)
res->limit = res->base + res->size -1;
res->align = 8;
res->gran = 8;
- res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
}
diff --git a/src/southbridge/intel/esb6300/esb6300_sata.c b/src/southbridge/intel/esb6300/esb6300_sata.c
index 5818df1819..6dce2d2f3a 100644
--- a/src/southbridge/intel/esb6300/esb6300_sata.c
+++ b/src/southbridge/intel/esb6300/esb6300_sata.c
@@ -15,37 +15,37 @@ static void sata_init(struct device *dev)
/* SATA configuration */
pci_write_config8(dev, 0x04, 0x07);
pci_write_config8(dev, 0x09, 0x8f);
-
+
/* Set timmings */
pci_write_config16(dev, 0x40, 0x0a307);
pci_write_config16(dev, 0x42, 0x0a307);
-
+
/* Sync DMA */
pci_write_config16(dev, 0x48, 0x000f);
pci_write_config16(dev, 0x4a, 0x1111);
-
+
/* 66 mhz */
pci_write_config16(dev, 0x54, 0xf00f);
-
+
/* Combine ide - sata configuration */
pci_write_config8(dev, 0x90, 0x0);
-
+
/* port 0 & 1 enable */
pci_write_config8(dev, 0x92, 0x33);
-
+
/* initialize SATA */
pci_write_config16(dev, 0xa0, 0x0018);
pci_write_config32(dev, 0xa4, 0x00000264);
pci_write_config16(dev, 0xa0, 0x0040);
pci_write_config32(dev, 0xa4, 0x00220043);
-
+
printk(BIOS_DEBUG, "SATA Enabled\n");
}
static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* This value is also visible in usb1, usb2 and smbus functions */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
@@ -66,7 +66,7 @@ static const struct pci_driver sata_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_6300ESB_SATA,
};
-
+
static const struct pci_driver sata_driver_nr __pci_driver = {
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_INTEL,
diff --git a/src/southbridge/intel/esb6300/esb6300_smbus.h b/src/southbridge/intel/esb6300/esb6300_smbus.h
index 0b793c37f9..e7a0d5c711 100644
--- a/src/southbridge/intel/esb6300/esb6300_smbus.h
+++ b/src/southbridge/intel/esb6300/esb6300_smbus.h
@@ -10,7 +10,7 @@
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
+#define SMBUS_PIN_CTL 0xf
#define SMBUS_TIMEOUT (100*1000*10)
diff --git a/src/southbridge/intel/esb6300/esb6300_uhci.c b/src/southbridge/intel/esb6300/esb6300_uhci.c
index 10b1dfa1cc..a8bcd888f1 100644
--- a/src/southbridge/intel/esb6300/esb6300_uhci.c
+++ b/src/southbridge/intel/esb6300/esb6300_uhci.c
@@ -12,7 +12,7 @@ static void uhci_init(struct device *dev)
#if 1
printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
+ pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_MASTER);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 20:38:26 +0000