diff options
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/lpc.c')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/lpc.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 8c1596725d..2fc3ea7e7b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -31,7 +31,12 @@ #include <arch/acpi.h> #include <cpu/cpu.h> #include <elog.h> +#include <arch/acpigen.h> +#include <drivers/intel/gma/i915.h> +#include <cbmem.h> +#include <string.h> #include "pch.h" +#include "nvs.h" #define NMI_OFF 0 @@ -625,6 +630,32 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void southbridge_inject_dsdt(void) +{ + global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + void *opregion; + + /* Calling northbridge code as gnvs contains opregion address. */ + opregion = igd_make_opregion(); + + if (gnvs) { + int scopelen; + + memset(gnvs, 0, sizeof (*gnvs)); + + acpi_create_gnvs(gnvs); + /* IGD OpRegion Base Address */ + gnvs->aslb = (u32)opregion; + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + scopelen = acpigen_write_scope("\\"); + scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_patch_len(scopelen - 1); + } +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -633,6 +664,8 @@ static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pch_lpc_enable_resources, + .write_acpi_tables = acpi_write_hpet, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = lpc_init, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, |