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Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x')
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/lpc.c33
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/nvs.h1
4 files changed, 37 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig
index b2b4929348..f628270b2b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Kconfig
+++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig
@@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
+ select PER_DEVICE_ACPI_TABLES
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl
index 2fe092d952..be1eafb1c7 100644
--- a/src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/fsp_bd82x6x/acpi/globalnvs.asl
@@ -31,8 +31,8 @@ Name(\DSEN, 1) // Display Output Switching Enable
* we have to fix it up in coreboot's ACPI creation phase.
*/
-
-OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00)
+External(NVSA)
+OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 8c1596725d..2fc3ea7e7b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -31,7 +31,12 @@
#include <arch/acpi.h>
#include <cpu/cpu.h>
#include <elog.h>
+#include <arch/acpigen.h>
+#include <drivers/intel/gma/i915.h>
+#include <cbmem.h>
+#include <string.h>
#include "pch.h"
+#include "nvs.h"
#define NMI_OFF 0
@@ -625,6 +630,32 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+static void southbridge_inject_dsdt(void)
+{
+ global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+ void *opregion;
+
+ /* Calling northbridge code as gnvs contains opregion address. */
+ opregion = igd_make_opregion();
+
+ if (gnvs) {
+ int scopelen;
+
+ memset(gnvs, 0, sizeof (*gnvs));
+
+ acpi_create_gnvs(gnvs);
+ /* IGD OpRegion Base Address */
+ gnvs->aslb = (u32)opregion;
+ /* And tell SMI about it */
+ smm_setup_structures(gnvs, NULL, NULL);
+
+ /* Add it to DSDT. */
+ scopelen = acpigen_write_scope("\\");
+ scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_patch_len(scopelen - 1);
+ }
+}
+
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
@@ -633,6 +664,8 @@ static struct device_operations device_ops = {
.read_resources = pch_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pch_lpc_enable_resources,
+ .write_acpi_tables = acpi_write_hpet,
+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.init = lpc_init,
.enable = pch_lpc_enable,
.scan_bus = scan_static_bus,
diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h
index 8889f02f27..8557c022e5 100644
--- a/src/southbridge/intel/fsp_bd82x6x/nvs.h
+++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h
@@ -156,3 +156,4 @@ typedef struct {
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
+void acpi_create_gnvs(global_nvs_t *gnvs);