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Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 3500dfd6e6..bc58b487c0 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -130,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x4f);
/* Load the ramstage. */