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path: root/src/southbridge/intel/i3100/i3100_pciexp_portb.c
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Diffstat (limited to 'src/southbridge/intel/i3100/i3100_pciexp_portb.c')
-rw-r--r--src/southbridge/intel/i3100/i3100_pciexp_portb.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i3100/i3100_pciexp_portb.c b/src/southbridge/intel/i3100/i3100_pciexp_portb.c
index a987da02f5..31502a46de 100644
--- a/src/southbridge/intel/i3100/i3100_pciexp_portb.c
+++ b/src/southbridge/intel/i3100/i3100_pciexp_portb.c
@@ -46,12 +46,12 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
int flag = 0;
do {
val = pci_read_config16(dev, PCIE_LSTS);
- printk_debug("pcie portb link status: %02x\n", val);
+ printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val);
if ((val & (1<<10)) && (!flag)) { /* training error */
ctl = pci_read_config16(dev, PCIE_LCTL);
pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
val = pci_read_config16(dev, PCIE_LSTS);
- printk_debug("pcie portb reset link status: %02x\n", val);
+ printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val);
flag=1;
hard_reset();
}