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Diffstat (limited to 'src/southbridge/intel/i82371eb/reset.c')
-rw-r--r--src/southbridge/intel/i82371eb/reset.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82371eb/reset.c b/src/southbridge/intel/i82371eb/reset.c
new file mode 100644
index 0000000000..baff05b143
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/reset.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "i82371eb.h"
+
+/**
+ * Initiate a hard reset.
+ */
+void i82371eb_hard_reset(void)
+{
+ outb(SRST | RCPU, RC);
+}