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Diffstat (limited to 'src/southbridge/intel/i82371eb')
-rw-r--r--src/southbridge/intel/i82371eb/early_smbus.c14
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.h1
2 files changed, 8 insertions, 7 deletions
diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c
index f69cb93a74..671bfc5854 100644
--- a/src/southbridge/intel/i82371eb/early_smbus.c
+++ b/src/southbridge/intel/i82371eb/early_smbus.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <console/console.h>
#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@@ -29,7 +28,12 @@ void i82371eb_early_init(void)
enable_pm();
}
-void enable_smbus(void)
+uintptr_t smbus_base(void)
+{
+ return SMBUS_IO_BASE;
+}
+
+int smbus_enable_iobar(uintptr_t base)
{
pci_devfn_t dev;
u8 reg8;
@@ -40,7 +44,7 @@ void enable_smbus(void)
PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
/* Set the SMBus I/O base. */
- pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
+ pci_write_config32(dev, SMBBA, base | 1);
/* Enable the SMBus controller host interface. */
reg8 = pci_read_config8(dev, SMBHSTCFG);
@@ -52,9 +56,7 @@ void enable_smbus(void)
reg16 |= PCI_COMMAND_IO;
pci_write_config16(dev, PCI_COMMAND, reg16);
- smbus_host_reset(SMBUS_IO_BASE);
-
- printk(BIOS_DEBUG, "SMBus controller enabled\n");
+ return 0;
}
int smbus_read_byte(u8 device, u8 address)
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index b292beb173..2b530102e3 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -19,7 +19,6 @@
#if !defined(__ACPI__)
-void enable_smbus(void);
void enable_pm(void);
void i82371eb_early_init(void);