diff options
Diffstat (limited to 'src/southbridge/intel/i82371eb')
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb_early_pm.c | 53 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb_early_smbus.c | 6 |
3 files changed, 56 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index cb4356ef8a..1093766dbe 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -72,5 +72,6 @@ void i82371eb_hard_reset(void); #define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ #define ISA (1 << 0) /* Select ISA */ #define EIO (0 << 0) /* Select EIO */ +#define PMIOSE (1 << 0) /* PM I/O Space Enable */ #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c new file mode 100644 index 0000000000..e6dd68eb7a --- /dev/null +++ b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/pci_ids.h> +#include "i82371eb.h" + +#define PM_IO_BASE 0xe400 + +static void enable_pm(void) +{ + device_t dev; + u8 reg8; + u16 reg16; + + /* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); + + if (dev == PCI_DEV_INVALID) + die("SMBus/PM controller not found\n"); + + /* Set the PM I/O base. */ + pci_write_config32(dev, PMBA, PM_IO_BASE | 1); + + /* Enable access to the PM I/O space. */ + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_IO; + pci_write_config16(dev, PCI_COMMAND, reg16); + + /* PM I/O Space Enable (PMIOSE). */ + reg8 = pci_read_config8(dev, PMREGMISC); + reg8 |= PMIOSE; + pci_write_config8(dev, PMREGMISC, reg8); +} + diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c index ada781ec26..76ae9f50b2 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c +++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c @@ -33,14 +33,12 @@ static void enable_smbus(void) u8 reg8; u16 reg16; - /* Check for SMBus device PCI ID on the 82371AB/EB/MB. */ + /* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); if (dev == PCI_DEV_INVALID) - die("SMBus controller not found\n"); - - print_spew("SMBus controller enabled\n"); + die("SMBus/PM controller not found\n"); /* Set the SMBus I/O base. */ pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); |