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Diffstat (limited to 'src/southbridge/intel/i82801bx/i82801bx.h')
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx.h39
1 files changed, 18 insertions, 21 deletions
diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h
index 70f573f96c..eae6de6d86 100644
--- a/src/southbridge/intel/i82801bx/i82801bx.h
+++ b/src/southbridge/intel/i82801bx/i82801bx.h
@@ -26,6 +26,13 @@
extern void i82801bx_enable(device_t dev);
#endif
+#define SMBUS_IO_BASE 0x0f00
+#define PMBASE_ADDR 0x0400
+#define GPIO_BASE_ADDR 0x0500
+#define HPET_ADDR 0xfed00000
+
+#define SECSTS 0x1e
+
#define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64
#define GEN_CNTL 0xd0
@@ -34,11 +41,12 @@ extern void i82801bx_enable(device_t dev);
#define GEN_PMCON_3 0xa4
#define PMBASE 0x40
-#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */
#define ACPI_CNTL 0x44
+#define ACPI_EN (1 << 4)
#define BIOS_CNTL 0x4E
-#define GPIO_BASE 0x58 /* LPC GPIO Base Address Register */
-#define GPIO_CNTL 0x5C /* LPC GPIO Control Register */
+#define GPIO_BASE 0x58 /* GPIO Base Address Register */
+#define GPIO_CNTL 0x5C /* GPIO Control Register */
+#define GPIO_EN (1 << 4)
#define PIRQA_ROUT 0x60
#define PIRQB_ROUT 0x61
@@ -51,10 +59,10 @@ extern void i82801bx_enable(device_t dev);
#define FUNC_DIS 0xF2
-#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */
-#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */
-#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */
-#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */
+#define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */
+#define LPC_EN 0xE6 /* LPC IF Enables Register */
+
+// TODO: FDC_DEC etc
#define SBUS_NUM 0x19
#define SUB_BUS_NUM 0x1A
@@ -67,8 +75,6 @@ extern void i82801bx_enable(device_t dev);
#define MTT 0x70
#define PCI_MAST_STS 0x82
-#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
-
#define TCOBASE 0x60 /* TCO Base Address Register */
#define TCO1_CNT 0x08 /* TCO1 Control Register */
@@ -77,14 +83,14 @@ extern void i82801bx_enable(device_t dev);
#define RTC_POWER_FAILED (1 << 1)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
-/* PCI Configuration Space (D31:F1) */
+/* IDE Timing registers (IDE_TIM) */
#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
/* IDE_TIM bits */
#define IDE_DECODE_ENABLE (1 << 15)
-/* PCI Configuration Space (D31:F3) */
+/* SMbus */
#define SMB_BASE 0x20
#define HOSTC 0x40
@@ -93,13 +99,7 @@ extern void i82801bx_enable(device_t dev);
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
-/* SMBus I/O bits.
- * TODO: Does it matter where we put the SMBus IO base, as long as we keep
- * consistent and don't interfere with anything else?
- */
-/* #define SMBUS_IO_BASE 0x1000 */
-#define SMBUS_IO_BASE 0x0f00
-
+/* SMBus I/O registers. */
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
@@ -114,8 +114,5 @@ extern void i82801bx_enable(device_t dev);
#define SMBUS_TIMEOUT (10 * 1000 * 100)
-/* HPET, if present */
-#define HPET_ADDR 0xfed00000
-
#endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */