summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801bx/reset.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/i82801bx/reset.c')
-rw-r--r--src/southbridge/intel/i82801bx/reset.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801bx/reset.c b/src/southbridge/intel/i82801bx/reset.c
new file mode 100644
index 0000000000..8d85cdca75
--- /dev/null
+++ b/src/southbridge/intel/i82801bx/reset.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+ /* Try rebooting through port 0xcf9. */
+ outb((1 << 2) | (1 << 1), 0xcf9);
+}