1 files changed, 32 insertions, 32 deletions
diff --git a/src/southbridge/intel/i82801ca/i82801ca.h b/src/southbridge/intel/i82801ca/i82801ca.h
index a5117f23b6..59056f29df 100644
--- a/src/southbridge/intel/i82801ca/i82801ca.h
+++ b/src/southbridge/intel/i82801ca/i82801ca.h
@@ -1,10 +1,10 @@
 #ifndef I82801CA_H
 #define I82801CA_H
-
-#ifndef __ROMCC__
+
+#ifndef __ROMCC__
 #include "chip.h"
-extern void i82801ca_enable(device_t dev);
-#endif
+extern void i82801ca_enable(device_t dev);
+#endif
 
 
 #define PCI_DMA_CFG     0x90
@@ -26,37 +26,37 @@ extern void i82801ca_enable(device_t dev);
 #define FUNC_DIS        0xF2
 
 // GEN_PMCON_3 bits
-#define RTC_BATTERY_DEAD		(1<<2)
-#define RTC_POWER_FAILED		(1<<1)
+#define RTC_BATTERY_DEAD		(1<<2)
+#define RTC_POWER_FAILED		(1<<1)
 #define SLEEP_AFTER_POWER_FAIL	(1<<0)
-
-/********************************************************************/
-/*							IDE Controller                          */
-/********************************************************************/
-
-// PCI Configuration Space (D31:F1)
-#define IDE_TIM_PRI		0x40		// IDE timings, primary
-#define IDE_TIM_SEC		0x42		// IDE timings, secondary
-
-
-// IDE_TIM bits
-#define IDE_DECODE_ENABLE	(1<<15)
-
-/********************************************************************/
-/*								SMBus                               */
-/********************************************************************/
-
-// PCI Configuration Space (D31:F3)
+
+/********************************************************************/
+/*							IDE Controller                          */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F1)
+#define IDE_TIM_PRI		0x40		// IDE timings, primary
+#define IDE_TIM_SEC		0x42		// IDE timings, secondary
+
+
+// IDE_TIM bits
+#define IDE_DECODE_ENABLE	(1<<15)
+
+/********************************************************************/
+/*								SMBus                               */
+/********************************************************************/
+
+// PCI Configuration Space (D31:F3)
 #define SMB_BASE	0x20
-#define HOSTC		0x40
-
-// HOSTC bits
-#define I2C_EN		(1<<2)
-#define SMB_SMI_EN	(1<<1)
-#define HST_EN		(1<<0)
+#define HOSTC		0x40
+
+// HOSTC bits
+#define I2C_EN		(1<<2)
+#define SMB_SMI_EN	(1<<1)
+#define HST_EN		(1<<0)
 
 #define SMBUS_IO_BASE 0x1000
-
+
 // I/O registers (relative to SMBUS_IO_BASE)
 #define SMBHSTSTAT		0
 #define SMBHSTCTL		2
@@ -69,7 +69,7 @@ extern void i82801ca_enable(device_t dev);
 #define SMBSLVDATA		10
 #define SMLINK_PIN_CTL	14
 #define SMBUS_PIN_CTL	15 
-
+
 /* Between 1-10 seconds, We should never timeout normally 
  * Longer than this is just painful when a timeout condition occurs.
  */