diff options
Diffstat (limited to 'src/southbridge/intel/i82801cx')
| -rw-r--r-- | src/southbridge/intel/i82801cx/chip.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801cx/i82801cx.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801cx/i82801cx.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801cx/i82801cx_early_smbus.c | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801cx/i82801cx_lpc.c | 38 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801cx/i82801cx_smbus.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801cx/i82801cx_usb.c | 4 |
7 files changed, 33 insertions, 33 deletions
diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h index 99b069e82d..88415e0556 100644 --- a/src/southbridge/intel/i82801cx/chip.h +++ b/src/southbridge/intel/i82801cx/chip.h @@ -1,7 +1,7 @@ #ifndef I82801CX_CHIP_H #define I82801CX_CHIP_H -struct southbridge_intel_i82801cx_config +struct southbridge_intel_i82801cx_config { }; extern struct chip_operations southbridge_intel_i82801cx_ops; diff --git a/src/southbridge/intel/i82801cx/i82801cx.c b/src/southbridge/intel/i82801cx/i82801cx.c index ddbbc7da37..685c931fc8 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.c +++ b/src/southbridge/intel/i82801cx/i82801cx.c @@ -19,7 +19,7 @@ void i82801cx_enable(device_t dev) // Calculate disable bit position for specified device:function // NOTE: For ICH-3, only the following devices can be disabled: - // D31:F1, D31:F3, D31:F5, D31:F6, + // D31:F1, D31:F3, D31:F5, D31:F6, // D29:F0, D29:F1, D29:F2 if (PCI_SLOT(dev->path.pci.devfn) == 31) { diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h index ea7d858d14..e0d377a9cd 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.h +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -70,9 +70,9 @@ void i82801cx_hard_reset(void); #define SMBTRNSADD 9 #define SMBSLVDATA 10 #define SMLINK_PIN_CTL 14 -#define SMBUS_PIN_CTL 15 +#define SMBUS_PIN_CTL 15 -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100*1000) diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c index 02420ef75b..b62db80f9c 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c @@ -10,9 +10,9 @@ static void enable_smbus(void) pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* Set smbus enable */ pci_write_config8(dev, HOSTC, HST_EN); - /* Set smbus iospace enable */ + /* Set smbus iospace enable */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation */ + /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -55,7 +55,7 @@ static int smbus_wait_until_ready(void) } if(loops == (SMBUS_TIMEOUT / 2)) { // Clear status flags - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } } while(--loops); @@ -69,7 +69,7 @@ static int smbus_wait_until_done(void) do { unsigned char val; smbus_delay(); - + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); // !HOST_BUSY? if ( (val & 1) == 0) { @@ -92,7 +92,7 @@ static int smbus_read_byte(unsigned device, unsigned address) if (smbus_wait_until_ready() < 0) { return -2; } - + /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c index 7523b03f80..97b2994abf 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c +++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c @@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1 -static void i82801cx_enable_ioapic( struct device *dev) +static void i82801cx_enable_ioapic( struct device *dev) { uint32_t dword; volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000; @@ -36,12 +36,12 @@ static void i82801cx_enable_ioapic( struct device *dev) dword |= (1 << 2); /* DMA collection buf enable */ pci_write_config32(dev, GEN_CNTL, dword); printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); - + // Must program the APIC's ID before using it *ioapic_index = 0; // Select APIC ID register *ioapic_data = (2<<24); - + // Hang if the ID didn't take (chip not present?) *ioapic_index = 0; dword = *ioapic_data; @@ -65,11 +65,11 @@ static void i82801cx_enable_serial_irqs( struct device *dev) // Parameters: dev // mask - identifies whether each channel should be used for PCI DMA // (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. -// Channel 4 is not used (reserved). +// Channel 4 is not used (reserved). // Return Value: None // Description: Route all DMA channels to either PCI or LPC. // -static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) +static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t dmaConfig; int channelIndex; @@ -105,13 +105,13 @@ static void i82801cx_rtc_init(struct device *dev) pmcon3 |= SLEEP_AFTER_POWER_FAIL; } pci_write_config8(dev, GEN_PMCON_3, pmcon3); - printk(BIOS_INFO, "set power %s after power fail\n", + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); // See if the Safe Mode jumper is set dword = pci_read_config32(dev, GEN_STS); rtc_failed |= dword & (1 << 2); - + rtc_init(rtc_failed); } @@ -120,28 +120,28 @@ static void i82801cx_1f0_misc(struct device *dev) { // Prevent LPC disabling, enable parity errors, and SERR# (System Error) pci_write_config16(dev, PCI_COMMAND, 0x014f); - + // Set ACPI base address to 0x1100 (I/O space) pci_write_config32(dev, PMBASE, 0x00001101); - + // Enable ACPI I/O and power management pci_write_config8(dev, ACPI_CNTL, 0x10); - + // Set GPIO base address to 0x1180 (I/O space) pci_write_config32(dev, GPIO_BASE, 0x00001181); - + // Enable GPIO pci_write_config8(dev, GPIO_CNTL, 0x10); - + // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); - + // Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted. pci_write_config8(dev, PIRQE_ROUT, 0x07); - + // Enable access to the upper 128 byte bank of CMOS RAM pci_write_config8(dev, RTC_CONF, 0x04); - + // Decode 0x3F8-0x3FF (COM1) for COMA port, // 0x2F8-0x2FF (COM2) for COMB pci_write_config8(dev, COM_DEC, 0x10); @@ -149,7 +149,7 @@ static void i82801cx_1f0_misc(struct device *dev) // LPT decode defaults to 0x378-0x37F and 0x778-0x77F // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 - // Enable COMA, COMB, LPT, floppy; + // Enable COMA, COMB, LPT, floppy; // disable microcontroller, Super I/O, sound, gameport pci_write_config16(dev, LPC_EN, 0x000F); } @@ -164,7 +164,7 @@ static void lpc_init(struct device *dev) i82801cx_enable_ioapic(dev); i82801cx_enable_serial_irqs(dev); - + /* power after power fail */ /* FIXME this doesn't work! */ /* Which state do we want to goto after g3 (power restored)? @@ -187,11 +187,11 @@ static void lpc_init(struct device *dev) byte = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { + if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70); } - + /* Initialize the real time clock */ i82801cx_rtc_init(dev); diff --git a/src/southbridge/intel/i82801cx/i82801cx_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_smbus.c index b69bbc1d9d..324f82f286 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_smbus.c @@ -9,7 +9,7 @@ void smbus_enable(void) { /* iobase addr */ - pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, + pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* smbus enable */ pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN); @@ -31,13 +31,13 @@ static void smbus_wait_until_ready(void) static void smbus_wait_until_done(void) { unsigned char byte; - + // Loop while HOST_BUSY do { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); } while((byte &1) == 1); - + // Wait for SUCCESS or error or BYTE_DONE while( (byte & ~1) == 0) { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); diff --git a/src/southbridge/intel/i82801cx/i82801cx_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c index 00b668d023..28cb3572e5 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_usb.c +++ b/src/southbridge/intel/i82801cx/i82801cx_usb.c @@ -12,8 +12,8 @@ static void usb_init(struct device *dev) uint32_t cmd; printk(BIOS_DEBUG, "USB: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + pci_write_config32(dev, PCI_COMMAND, + cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); |